Abstract
Both enhancement and depletion n-channel MOS devices with electrical channel lengths between 1 and 0.3 µm are characterized in terms of carrier heating effects. The effect of gate oxide thickness on the two-dimensional (2-D) electric field distribution has been analyzed through 2-D numerical device simulation, and its impact on carrier heating process has been experimentally quantified. Our results allow some conclusions for reduced supply voltages (2 and 3 V for temperatures of 77 and 300 K, respectively) for future NMOS technologies with design rules of 0.75 µm.
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