Submicrometer Gate Lengths Research Articles

Scaling properties and short-channel effects in submicrometer AlGaAs/GaAs MODFET's: A Monte Carlo study

Scaling properties of n/sup +/-Al/sub x/Ga/sub 1-x/As/GaAs MODFETs with submicrometer gate lengths (L/sub G/=0.50 to 0.05 mu m) are examined, using Monte Carlo methods. High-frequency performance of MODFETs can be improved by scaling the gate lengths, but various studies suggest that there exists a lower limit for the gate after which no improvement should be expected. The lower limit is determined here to be approximately=0.10 mu m. Devices with smaller gate lengths than 0.1 mu m exhibit degraded transconductance (g/sub m/), large shift in threshold voltage due to poor charge control in the channel, and a sharp reduction in output resistance (R/sub o/). It is shown that the drain current saturation in MODFETs is not caused by the velocity saturation effect, but by channel pitch-off. Electron velocities calculated from Monte Carlo simulations and extracted from g/sub m/ and f/sub t/ measurements are reconciled. >

Suppression of parasitic bipolar effects in thin-film SOI transistors

In order to correctly estimate the bipolar holding voltage of thin-film SOI transistors with submicrometer gate lengths, it is necessary to obtain the correct balance between the bipolar current gain and impact ionization. The bipolar current gain was found to be strongly dependent upon bandgap narrowing in the heavily doped source, while impact ionization may be most accurately modeled with a nonlocal ballistic model employing a composite electron mean-free path of 9.2 nm. Simulation with the improved models suggests that a reduction in the lateral electric field of the n/sup -/ drain region, and hence an increased bipolar holding voltage, may be achieved by using ultrathin highly doped SOI films. For a 0.5- mu m gate length, a maximum holding voltage in excess of 6 V has been simulated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices

The tradeoff between circuit performance and reliability is theoretically and experimentally examined in detail, down to half-micrometer and lower submicrometer gate lengths, taking into account high-field effects on MOSFETs. Some guidelines for optimum power-supply voltage and process/device parameters for half-micrometer and lower submicrometer CMOS devices are proposed in order to maintain MOS device reliability and achieve high circuit performance. It is shown that power-supply voltage must be reduced to maintain reliability and improved performance and that the optimum voltage reduction follows the square root of the design rule. Trends for scaling down power-supply voltage have been experimentally verified by results obtained from measurements on CMOS devices over a wide range of gate oxide thickness (7-45 nm) and gate lengths (0.3-2.0 mu m). >

A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers

A circuit design technique for suppressing asymmetrical characteristics in a high-density DRAM sense amplifier is discussed, and the effect of drain current imbalances between transistor pairs and the sensitivity of the sense amplifier are studied experimentally. A sense amplifier composed of parallel transistor pairs which have a reversed source and drain arrangement on a wafer is capable of suppressing the asymmetry effects to less than 15 mV in a range of submicrometer gate lengths and of reducing the layout area by about 43% compared with the conventional sense amplifier. >

A GaAs MESFET small-signal equivalent circuit including transmission line effects

A small-signal equivalent circuit for the GaAs MESFET, suitable for the design of integrated circuits, was developed that includes the following features: (1) at high frequencies, the gate channel has the character of an RC transmission line, for which a pi -equivalent representation is used; (2) under saturated current conditions, a stationary high-field domain may be present in the conducting channel, for which an equivalent is derived in terms of a small-signal admittance. The resulting equivalent circuit was optimized with very good results by modeling process average S-parameters between 1 and 25 GHz for a 1 mu m gate device. The basic structure of the model is relevant for other FET designs such as heterostructure FETs (HEMTs) and devices with submicrometer gate lengths.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design considerations for thin-film SOI/CMOS device structures

Allowable design regions for thin-film SOI/CMOs device structures, taking account for the relation between SOI film thickness and the concentration of SOI substrate impurities, are investigated. Not only are the advantages of thin-film SOI MOSFETs verified, but constraints on threshold voltage and kink-free controls are also shown. Conventional n/sup +/ poly-Si gate NMOSFETs tend to have difficulty in maintaining high transconductance for deep submicrometer gate length because of the constraints of normally-off threshold voltage and kink-free characteristics. By choosing a gate with the same work function as the intrinsic silicon semiconductor, the allowable design regions for deep submicrometer gate SOI MOSFETs are expected to have a low-impurity SOI substrate and an optimized threshold voltage for high-performance SOI/CMOS LSIs. The device scaling for various gate electrodes are also discussed for 1- to 0.2 mu m gate SOI/CMOS devices. >

Traveling-wave inverted-gate field-effect transistors: concept, analysis, and potential

A unified approach to the analysis of the traveling-wave inverted-gate FET (INGFET) is presented. The equivalent circuit parameters of the GaAs inverted-gate FET, with submicrometer gate length, are obtained using a two-dimensional computer model which takes into account the nonstationary electron dynamics. The parameters of the passive transmission line, corresponding to the INGFET structure, are obtained using a quasi-transverse-electromagnetic (TEM) wave approach. The conductor losses of this structure are estimated using the incremental inductance rule. The coupled mode theory is used to derive the wave equation describing this traveling-wave transistor. The results show the existence of a rapidly growing mode along the device electrodes. It is also shown that this mode can be excited alone by appropriate matching and feeding arrangements. Improper matching and feeding lead to a narrower bandwidth due to the resonance phenomenon of the resulting standing wave. >

A MOSFET tetrode with 0.4 μm gates fabricated by mixed exposure of X-ray and DUV lithography

Using the synchrotron radiation of the Berlin Electron Storage Ring (BESSY) and conventional UV 400 contact lithography a MOSFET tetrode with submicrometer gate length was fabricated. X-ray lithography has been applied therefore in two resist processes to define the gate lengths and the metallization (contact) level. The employed X-ray masks are based on stress compensated Si membranes with electroplated gold absorber structures. The mask flatness and the pattern distortions are smaller than 3 μm and 100 nm respectively and are adequate for achieving a high yield of transistors.

An advanced single-level polysilicon submicrometer BiCMOS technology

An advanced VLSI (very large scale integration) technology providing high-performance n-p-n bipolar (f/sub T/=9 GHz) and submicrometer gate-length MOS (metal-oxide-semiconductor) transistors is described. This technology is intended for high-speed logic circuits operating at 5 V, where a high level of circuit integration and low power consumption is required. Features include vertical n-p-n transistors with walled, self-aligned polysilicon emitters and lightly doped extrinsic base (LDEB) extensions MOS transistors feature complementary-doped polysilicon gates and LDD (lightly doped drain) structures for both NMOS and PMOS. Optional buried contacts between the polysilicon layer and all junctions in the silicon substrate are provided. Polysilicon emitters, MOS gates, base/collector, and source/drain regions are silicided. In addition, a fully planarized metal interconnect scheme incorporating nonselective CVD (chemical-vapor-deposited) tungsten and vertical-walled contacts and vias is utilized. >

High-speed enhancement-mode InP MISFET's grown by chloride vapor-phase epitaxy

The properties of enhancement-mode InP metal-insulator-semiconductor field-effect transistors fabricated on semi-insulating InP substrates are reported. The epitaxial layers of the device structure have been grown by chloride vapor-phase epitaxy. Short-circuit current gain cutoff frequencies of 29.6 GHz were measured for 1- mu m-gate-length devices. For devices with submicrometer gate lengths, extrinsic transconductance values up to 300 mS/mm and short-circuit current-gain cutoff frequencies of 38.1 GHz were measured. SiO/sub 2/ deposited by electron beam evaporation and plasma-enhanced CVD Si/sub 3/N/sub 4/ have been utilized as gate insulators, and a drain current drift of 30% within the first 50 h of operation has been observed. The high-speed performance of these devices represent to the authors' knowledge the fastest InP-based MIS field-effect transistor demonstrated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A shallow junction submicrometer PMOS process without high temperature anneals

A PMOS process resulting in very shallow, low-leakage source-drain junctions without high-temperature annealing following doping is discussed. The doping is performed using gas immersion laser doping which relies on a melt/regrowth process, initiated by a pulsed excimer laser (XeCl, lambda =308 nm), to drive in the dopant species. The properties of the resulting source/drain layers are discussed. A significant feature of this process is that unwanted diffusions are eliminated because no high-temperature anneals are used after the doping step. Submicrometer PMOS devices fabricated using this process exhibit excellent short-channel behavior with some process conditions resulting in very little or no threshold-voltage shift down to submicrometer gate lengths. >

Studies on an In0.53Ga0.47As/In0.52Al0.48As single-quantum-well quasi-MISFET

We describe here the properties of a novel InGaAs/ InAlAs quasi-MISFET in which an inverted modulation-doped single quantum well forms the channel and an undoped semi-insulating InAlAs constitutes the gate barrier. The entire structure is grown lattice-matched to InP continuously by molecular-beam epitaxy in a single step. Rapid thermal annealing of implanted semiconductors and ohmic contacts have been investigated and have been used successfully in the fabrication of the MISFET's. Improved performance is obtained with the incorporation of Ti in the source-drain metallization, with which contact resistances as low as 0.1 ω . mm are measured. Charge-control modeling of the proposed device predicts the carrier concentration in the channel region fairly well at room temperature. A quantum mechanical modeling of the device in the effective mass approximation also has been done. The thickness of the InAlAs doping layer is found to be an important parameter that controls the device turn-on characteristics. The velocity-field characteristics of the two-dimensional channel electrons were measured by pulse current-voltage and pulsed Hall techniques. The maximum velocities measured at 300 and 77 K are 1.5 × 107and 1.7 × 107cm/s, respectively. Fairly high electron mobilities are measured in single-quantum-well MISFET structures even with well thicknesses as small as 100 A. The InAlAs gate barrier is effective in reducing the gate leakage current. Gate leakage currents are reduced further with a composite dielectric consisting of oxidized Al and InAlAs. An extrinsic transconductance of 310 mS/mm is measured in a 1.0-µm gate device at 300 K. A value of f T = 32 GHz, measured in a 1.0-µm device, is the best obtained so far with this material system. It is expected that submicrometer gate lengths will lead to even better performance.

Fabrication of submicrometer CMOS circuits using a new trilayer photolithographic process

CMOS circuits with submicrometer gate lengths were fabricated using a new trilayer photolithographic process. A transparent and electrically conductive film of indium tin oxide was used as the middle layer in the trilayer resist with unique advantages. The shortest on-mask gate length for which CMOS circuits were successfully fabricated was 0.75 µm. The corresponding effective channel lengths for NMOS and PMOS were on the order of 0.55 and 0.4 µm, respectively. A propagation delay of 106 ps at 5 V was achieved for CMOS ring oscillators fabricated using this process technology.

High-efficiency GaInAs Microwave MISFET's

GaInAs metal-insulator-semiconductor FET's (MISFET's) fabricated with a self-aligned-gate process and 1-µm gate lengths gave power outputs as high as 857 (1.53), 424 (0.76), 415 (0.74), and 114 mW (0.20 W/mm) at 4, 12, 20 and 32.5 GHz, respectively. Power-added efficiencies of 64.3 and 55.0 percent were obtained at 4 and 12 GHz, respectively. At 20 GHz, a power-added efficiency of 32.5 percent was obtained. The value of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f_{\max}</tex> calculated from measured scattering parameters (S parameters) was ∼ 45 GHz. This high cutoff frequency was validated by the measured performance at 32.5 GHz. We believe this to be the best microwave performance reported for GaInAs power transistors. A self-aligned-gate process, essential for minimizing gate overlap capacitances while maintaining a full-gate structure, that offers the potential for Submicrometer gate-length device fabrication is described.

Two-layer resist structure for electron-beam fabrication of a submicrometer gate length GaAs device

A two-layer resist structure using EBR-9 and PMMA for fabricating a fine metal line with a mushroom-like cross-sectional profile is reported. The structure provides T-shaped resist cavities with undercut profiles using electron-beam exposure. With the optimum developing condition, the bottom opening is as small as 0.1 µm, and the top opening is wide enough not to require an additional exposure in order to obtain a mushroom-like metal lift-off pattern. A Monte Carlo calculation is carried out in order to analyze the profile of the two-layer resist structure, and it is shown that an undercut T-shaped resist profile with a 0.1-µm bottom opening can be obtained using a high-sensitivity resist on a low-sensitivity resist structure. A 0.15-µn mushroom-like lift-off metal profile has been fabricated on a 0.1-µm recessed GaAs substrate by the use of this resist structure.

A submicrometer lifted diffused-layer MOSFET

A new lifted diffused-layer (LID) MOSFET has been devised and fabricated, where the major portions of the source/drain (S/ D) diffused layers are placed on top of the field insulator to reduce S/D parasitic capacitances. The primary feature of this MOSFET is that the structure and processing are especially developed for submicrometer gate lengths. The fabricated LID MOSFET with a 0.5-µm gate length and a 10-nm gate oxide thickness showed good electrical characteristics, such as a maximum transconductance of 115 mS/mm and an inverter delay time of 59 ps/stage.

A high-speed high-density silicon 8×8-bit parallel multiplier

An 8/spl times/8-bit parallel multiplier with submicrometer gate lengths has been fabricated using silicon NMOS technology. The multiplication time is 9.5 ns. This corresponds to an average loaded gate delay in the multiplier circuit of 244 ps/gate, which the authors believe is the shortest gate delay for MOS multiplier circuits demonstrated to date. The power dissipation is 600 mW at a supply voltage of 5 V. The multiplier circuit has a total of 1427 transistors in an active area of 0.61/spl times/0.58 mm/SUP 2/, corresponding to a gate density of 1125 gates/mm/SUP 2/.

Determination of effective saturation velocity in n+self-aligned GaAs MESFET's with submicrometer gate lengths

The dependence of effective saturation velocity on gate length in n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> self-aligned GaAs MESFET's with submicrometer gate lengths has been determined by comparing experimental <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</tex> characteristics with that obtained from one-dimensional analysis and two-dimensional simulation. The experimental <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</tex> characteristics have been precisely matched to the theoretical ones calculated by two-dimensional simulation with a quasi-static (effective) velocity-electric-field relationship and reasonable doping profiles. The effective saturation velocity determined by best fit is 2.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cm/s, and is independent of the gate length in 0.3- to 1.0-µm range. Though this high value gives evidence of the velocity overshoot effects, the constant characteristic disagrees with the expectation of the simulations based on nonstationary electron transport. On the contrary, the saturation velocity determined by using one-dimensional analysis decreases with an increase in the gate length. This dependence is explained by taking into account the channel pinchoff mechanism for drain current saturation before velocity saturation.

Self-aligned half-micrometer Silicon MASFET's with metallic amorphous Silicon gate

Ternary metallic amorphous silicon (a-Si-Ge-B), having a high barrier height feature with crystalline semiconductors is applied to the gate metal of Si MESFET's. A submicrometer gate length is successfully fabricated using a self-aligned technology and a conventional photolithography. A large transconductance above 130 mS/mm under the normally-OFF state and a small standard deviation of threshold voltage less than 11 mV are realized for a 0.5-µm gate-length device across a 4-in-diameter wafer. A minimum delay time of 114 ps/gate with an associated switching energy of 1.6 pJ and a minimum switching energy of 3.3 fJ with a delay time of 26 ns/gate are attained by a 21-stage ring oscillator with E/R direct-coupled FET logic circuits.

Fabrication of submicrometer MOSFET's using gas immersion laser doping (GILD)

The fabrication of MOSFET's with submicrometer gate lengths using Gas Immersion Laser Doping (GILD) to dope the source-drain and gate regions of n-channel devices is described. The GILD step relies on a melt/regrowth process, initiated by a pulsed excimer laser (XeCl, λ = 308 nm), to drive in a dopant species adsorbed on the clean silicon surface. High dopant concentrations (1 × 1019to 2 × 1021cm-3) and shallow junctions (600-1000 A) make this process ideally suited for source-drain formation in submicrometer structures. In this work the transistors are fabricated using an otherwise conventional NMOS process. The resultant devices have similar source-drain R sheet values and lower poly R sheet when compared to devices fabricated using a conventional implanted source-drain and diffused polysilicon gate. Short-channel devices ( L_{poly} = 0.9 µm) exhibit excellent I-V characteristics and little change in V t .