Submicrometer Channel Length Research Articles

Approaching the Intrinsic Limits of Short Channel Vertical Organic Electrochemical Transistors.

Vertical architectures for organic electrochemical transistors (OECTs), due to their submicrometer channel lengths, have presented themselves as a straightforward design approach for achieving high gm/τ ratios, a figure of merit that assesses the performance of the devices by virtue of their transconductance (gm = dID/dVGS) and switching time constant (τ). However, as the practical limitations of the geometries are overcome, the influence of parasitic phenomena becomes more dominant and limits the performance of the device. One approach to reduce the detrimental effects of parasitic resistance in the drain-source circuit is to use a four-point sourcing technique. Here, vertical OECTs are fabricated with four-point structures to approach the intrinsic limit of these devices. It is shown that this approach improves the saturation behavior of the devices, closing the gap between measured gm and intrinsic transconductance gmi at their peak values. Overall, the results discussed here provide insight into the effects of parasitic resistance on OECTs, which in contrast to field-effect transistors, are not as extensively documented.

A simple lithography-free approach for the fabrication of top-contact OFETs with sub-micrometer channel length

A simple lithography-free approach for the fabrication of top-contact OFETs with sub-micrometer channel length

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2.

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS2. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performed ex situ and transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.

Simultaneous Extraction of the Grain Size, Single-Crystalline Grain Sheet Resistance, and Grain Boundary Resistivity of Polycrystalline Monolayer Graphene.

The electrical properties of polycrystalline graphene grown by chemical vapor deposition (CVD) are determined by grain-related parameters—average grain size, single-crystalline grain sheet resistance, and grain boundary (GB) resistivity. However, extracting these parameters still remains challenging because of the difficulty in observing graphene GBs and decoupling the grain sheet resistance and GB resistivity. In this work, we developed an electrical characterization method that can extract the average grain size, single-crystalline grain sheet resistance, and GB resistivity simultaneously. We observed that the material property, graphene sheet resistance, could depend on the device dimension and developed an analytical resistance model based on the cumulative distribution function of the gamma distribution, explaining the effect of the GB density and distribution in the graphene channel. We applied this model to CVD-grown monolayer graphene by characterizing transmission-line model patterns and simultaneously extracted the average grain size (~5.95 μm), single-crystalline grain sheet resistance (~321 Ω/sq), and GB resistivity (~18.16 kΩ-μm) of the CVD-graphene layer. The extracted values agreed well with those obtained from scanning electron microscopy images of ultraviolet/ozone-treated GBs and the electrical characterization of graphene devices with sub-micrometer channel lengths.

High-Performance Ultra-Short Channel Field-Effect Transistor Using Solution-Processable Colloidal Nanocrystals.

We demonstrate high-mobility solution-processed inorganic field-effect transistors (FETs) with ultra-short channel (USC) length using semiconductor CdSe nanocrystals (NCs). Capping of the NCs with hybrid inorganic-organic CdCl3--butylamine ligands enables coarsening of the NCs during annealing at a moderate temperature, resulting in the devices having good transport characteristics with electron mobilities in the saturation regime reaching 8 cm2 V-1 s-1. Solution-based processing of the NCs and fabrication of thin films involve neither harsh conditions nor the use of hydrazine. Employing photolithographic methods, we fabricated FETs with a vertical overlap of source and drain electrodes to achieve a submicrometer channel length. To the best of our knowledge, this is the first report on an USC FET based on colloidal semiconductor NCs. Because of a short channel length, the FETs show a normalized transconductance of 4.2 m V-1 s-1 with a high on/off ratio of 105.

High-Performance Sub-Micrometer Channel WSe2 Field-Effect Transistors Prepared Using a Flood-Dike Printing Method.

Printing technology has potential to offer a cost-effective and scalable way to fabricate electronic devices based on two-dimensional (2D) transition metal dichalcogenides (TMDCs). However, limited by the registration accuracy and resolution of printing, the previously reported printed TMDC field-effect transistors (FETs) have relatively long channel lengths (13-200 μm), thus suffering low current-driving capabilities (≤0.02 μA/μm). Here, we report a "flood-dike" self-aligned printing technique that allows the formation of source/drain metal contacts on TMDC materials with sub-micrometer channel lengths in a reliable way. This self-aligned printing technique involves three steps: (i) printing of gold ink on a WSe2 flake to form the first gold electrode, (ii) modifying the surface of the first gold electrode with a self-assembled monolayer (SAM) to lower the surface tension and render the surface hydrophobic, and (iii) printing of gold ink close to the SAM-treated first electrode at a certain distance. During the third step, the gold ink would first spread toward the edge of the first electrode and then get stopped by the hydrophobic SAM coating, ending up forming a sub-micrometer channel. With this printing technique, we have successfully downscaled the channel length to ∼750 nm and achieved enhanced on-state current densities of ∼0.64 μA/μm (average) and high on/off current ratios of ∼3 × 105 (average). Furthermore, with our high-performance printed WSe2 FETs, driving capabilities for quantum-dot light-emitting diodes (LEDs), inorganic LEDs, and organic LEDs have been demonstrated, which reveals the potential of using printed TMDC electronics for display backplane applications.

Reverse‐Offset Printing Optimized for Scalable Organic Thin‐Film Transistors with Submicrometer Channel Lengths

Printed organic thin-film transistor (TFT) devices with submicrometer (0.6 μm) channel length (L) are fabricated by employing a scalable reverse-offset printing method. The fabricated TFT devices exhibit remarkable performance, with high field-effect mobilities (0.27 cm2 V−1 s−1 for L = 2.4 and 9.0 × 10−3 cm2 V−1 s−1 for L = 0.6 μm) and high on/off current ratios (>105). As a service to our authors and readers, this journal provides supporting information supplied by the authors. Such materials are peer reviewed and may be re-organized for online delivery, but are not copy-edited or typeset. Technical support issues arising from supporting information (other than missing files) should be addressed to the authors. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.

Modeling of Self-Aligned Vertical ZnO Thin-Film Transistors

Vertical zinc oxide (ZnO) thin-film transistors (TFTs) with submicrometer channel length have good performance, including large current density (>10 mA/mm), high mobility (> 14 cm $^{2}$ /Vs), and large current ON–OFF ratio ( $>10^{7})$ . They also have asymmetric current–voltage ( $I$ – $V$ ) characteristics in the saturation region when the source and drain electrodes are interchanged. We have used 2-D simulations with the Synopsis Sentaurus Device to model vertical ZnO TFTs. The devices studied in this paper had ZnO active layers deposited using spatial atomic layer deposition (SALD). Model parameters were calibrated by matching simulation results with experimental results of planar bottom-gate ZnO TFTs and further adjusted to fit vertical TFT (VTFT) experimental characteristics. We find we need acceptor-like traps above and below the conduction band minimum to model the SALD ZnO semiconductor behavior; in this paper, we introduced these as bulk traps. We find the asymmetric $I$ – $V$ characteristics arise from an ungated region near the foot of the VTFT, and which has a more significant effect on charge injection than on charge extraction. Modeling TFTs with different ungated region lengths gave good agreement with experimental characteristics.

Hot spot dynamics in carbon nanotube array devices.

We report on the dynamics of spatial temperature distributions in aligned semiconducting carbon nanotube array devices with submicrometer channel lengths. By using high-resolution optical microscopy in combination with electrical transport measurements, we observe under steady state bias conditions the emergence of time-variable, local temperature maxima with dimensions below 300 nm, and temperatures above 400 K. On the basis of time domain cross-correlation analysis, we investigate how the intensity fluctuations of the thermal radiation patterns are correlated with the overall device current. The analysis reveals the interdependence of electrical current fluctuations and time-variable hot spot formation that limits the overall device performance and, ultimately, may cause device degradation. The findings have implications for the future development of carbon nanotube-based technologies.

Implementation of Film Profile Engineering in the Fabrication of ZnO Thin-Film Transistors

A novel approach, which can delicately form a desirable film profile for deposited gate oxide, channel, and source/drain contacts of oxide-based thin-film transistors (TFTs) is proposed. To demonstrate the film-profile engineering concept used in this approach, a simple one-mask process was developed for fabricating ZnO TFTs with submicrometer channel length. The fabrication takes advantage of a suspended bridge hanging across the device to tailor the desirable profile of deposited films with proper tools. The fabricated devices show high ON/OFF current ratio (>109), steep subthreshold swing (71-187 mV/decade), and high mobility (21-45 cm2/V·s). Very small variation in device characteristics among the devices with the same channel dimensions is also confirmed.

Inkjet Printing Short‐Channel Polymer Transistors with High‐Performance and Ultrahigh Photoresponsivity

Inkjet-printed short-channel polymer transistors exhibit a high performance (μavg = 1.20 cm(2) V(-1) s(-1) ). With a 50 μm orifice nozzle, polymer transistors with a sub-micrometer (700 nm) channel length are mass-fabricated with good uniformity and reproducibility. In addition, owing to the device geometry, an ultrahigh photoresponsivity up to 10(6) A W(-1) is achieved, which realizes economical, lithography-free photodetectors.

High performance submicrometer pentacene-based organic thin-film transistor using planar bottom-contact structure

This paper presents a pentacene-based organic thin-film transistor (OTFT) with a submicrometer channel length of 0.5μm that uses a planar bottom-contact (pBC) structure to achieve high electrical performance. The performance of the submicrometer OTFT is dominantly influenced by the growth continuity of pentacene near the edge of the source/drain (S/D). The pBC structure with a bilayer dielectric can provide a continuous plane for improving the growth continuity and quality of pentacene near the edge of the S/D. This results in high electrical performance for the submicrometer OTFT with pBC structure, such as a mobility of 0.14cm2/Vs and an on/off current ratio of 1.9×105.

Fabrication of High-Performance ZnO Thin-Film Transistors With Submicrometer Channel Length

A method was developed to fabricate ZnO thin-film transistors (TFTs) with submicrometer channel length. In this scheme, mature process techniques are used to form a suspending hardmask bridge on the wafer surface, which enables the subsequent construction of a TFT by the sequential deposition of gate oxide, ZnO channel layer, and Al source/drain contacts. Excellent electrical characteristics were demonstrated by the fabricated ZnO TFTs that show high ON/OFF current ratio , low subthreshold swing (89 mV/decade), and high field-effect mobility (41 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V s). Very small variation in the device characteristics is also demonstrated.

Flexible Self-Aligned Amorphous InGaZnO Thin-Film Transistors With Submicrometer Channel Length and a Transit Frequency of 135 MHz

Flexible large area electronics promise to enable new devices such as rollable displays and electronic skins. Radio frequency (RF) applications demand circuits operating in the megahertz regime, which is hard to achieve for electronics fabricated on amorphous and temperature sensitive plastic substrates. Here, we present self-aligned amorphous indium-gallium-zinc oxide-based thin-film transistors (TFTs) fabricated on free-standing plastic foil using fabrication temperatures . Self-alignment by backside illumination between gate and source/drain electrodes was used to realize flexible transistors with a channel length of 0.5 μm and reduced parasitic capacities. The flexible TFTs exhibit a transit frequency of 135 MHz when operated at 2 V. The device performance is maintained when the TFTs are bent to a tensile radius of 3.5 mm, which makes this technology suitable for flexible RFID tags and AM radios.

Design and modeling of self-aligned nano-imprinted sub-micrometer pentacene-based organic thin-film transistors

Sub-micrometer channel length (0.5μm) organic thin-film transistors (OTFTs) are demonstrated using a process flow combining nano-imprint lithography (NIL) and self-alignment (SA). A dedicated test structure was designed and samples were fabricated on 4-in. plastic foils using a p-type sublimated small molecule (pentacene) as semiconductor. Field-effect mobilities, in saturation, between 0.1 and 1cm2/Vs were obtained not only for the supermicron OTFTs but also for the submicron OTFTs. Those devices were used to select a model based on the “TFT Generic Charge Drift model” which works well for a broad range of channel lengths including the submicron OTFTs. We show that these OTFTs can be accurately modeled, thus giving access to complex circuit simulations and design.

Analog Behavior of Submicron Graded-Channel SOI MOSFETs Varying Channel Length, Doping Concentration and Temperature

In this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductorswere used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature.

Length and temperature dependent 1/f noise in vertical single-walled carbon nanotube arrays

We report measurements of temperature- and length-dependent 1/f noise in vertical single-walled carbon nanotube (SWCNT) arrays. Carbon nanotubes are synthesized in a porous anodic alumina template with sub-micrometer channel lengths ranging from 100 to 700 nm. A significant difference is observed in the 1/f noise magnitude of quasi-ballistic and diffusive SWCNT devices, with quasi-ballistic devices exhibiting 1/f noise levels that are one to two orders of magnitude less than diffusively conducting devices. Furthermore, 1/f noise was measured from 90 to 400 K, and the noise prefactor decreased significantly at temperatures below 250 K.

High Current, Low Voltage Carbon Nanotube Enabled Vertical Organic Field Effect Transistors

State-of-the-art performance is demonstrated from a carbon nanotube enabled vertical field effect transistor using an organic channel material. The device exhibits an on/off current ratio >10(5) for a gate voltage range of 4 V with a current density output exceeding 50 mA/cm(2). The architecture enables submicrometer channel lengths while avoiding high-resolution patterning. The ability to drive high currents and inexpensive fabrication may provide the solution for the so-called OLED backplane problem.

Geometrical effect in submicrometer channel organic field effect transistors

The electrical behaviors of submicrometer bottom-gate bottom-contact organic field effect transistors (OFETs) with submicrometer channel lengths and channel widths were investigated. Short-channel effects (SCEs) were observed for devices with shorter channel lengths and wider channel widths. The SCEs were effectively suppressed by reducing the channel width to 50 nm. The relationship between the drain current density and the drain voltage normalized by their respective channel lengths revealed that the drain current characteristics of shorter length channels fall into two types: parasitic contact resistances at lower drain voltage and SCEs caused by the space charge limiting current at higher drain voltages. The carrier mobility was also investigated, and found to be enhanced in the narrower channel width.

High-Frequency Performance of Submicrometer Transistors That Use Aligned Arrays of Single-Walled Carbon Nanotubes

The unique electronic properties of single-walled carbon nanotubes (SWNTs) make them promising candidates for next generation electronics, particularly in systems that demand high frequency (e.g., radio frequency, RF) operation. Transistors that incorporate perfectly aligned, parallel arrays of SWNTs avoid the practical limitations of devices that use individual tubes, and they also enable comprehensive experimental and theoretical evaluation of the intrinsic properties. Thus, devices consisting of arrays represent a practical route to use of SWNTs for RF devices and circuits. The results presented here reveal many aspects of device operation in such array layouts, including full compatibility with conventional small signal models of RF response. Submicrometer channel length devices show unity current gain (f(t)) and unity power gain frequencies (f(max)) as high as approximately 5 and approximately 9 GHz, respectively, with measured scattering parameters (S-parameters) that agree quantitatively with calculation. The small signal models of the devices provide the essential intrinsic parameters: saturation velocities of 1.2 x 10(7) cm/s and intrinsic values of f(t) of approximately 30 GHz for a gate length of 700 nm, increasing with decreasing length. The results provide clear insights into the challenges and opportunities of SWNT arrays for applications in RF electronics.