Subthreshold Region Research Articles

Proposed time‐mode wide fan‐in NAND and NOR gates

SummaryCMOS circuits usually operate either in the voltage, current, charge, or time domain. Each of these domains has its own features. As the fan‐in of CMOS circuits increases, the performance of circuits that operate in the voltage domain, the current domain, or the charge domain degrades. This is the case especially with scaling down the power‐supply voltage associated with technology scaling. In this paper, a time‐mode scheme that utilizes a floating‐gate MOSFET (FGMOS) transistor is proposed. The proposed scheme showed good performance for wide fan‐in NAND and NOR gates. The design issues of the proposed scheme like the speed and the power consumption are investigated quantitatively. The performance of the proposed scheme is confirmed through simulation using the 45‐nm CMOS predictive technology model (PTM) with a 1‐V power‐supply voltage. 64‐input NAND and NOR gates realized using this scheme have time delays of 0.375 and 0.25 ns, respectively, at a load capacitance of 5 fF. The application of the proposed scheme for realizing multiplexers required in register files is illustrated and compared with the conventional domino logic in the superthreshold, near‐threshold, and subthreshold regions.

A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application.

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 μW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process.

A high-performance wordline voltage-generating system for low-power low-voltage flash memory

Wordline (WL) voltage-generating system is a crucial block in flash memory. It generates a voltage higher than the supply voltage for reading, programming and erasing in flash memory. However, operation accuracy is deteriorated by the excessive overshoot and ripple voltage. Moreover, current consumption in standby mode shortens the life of memory. The paper presents a high-performance wordline voltage-generating system in 55nm CMOS technology. In active mode, a variable stage and frequency charge pump system is proposed to suppress overshoot and ripple of WL voltage (VWL) when the supply voltage ranges from 1.5V to 2.1V. To cut down standby current, an ultra-low power voltage reference circuit operating in subthreshold region is introduced. When recovering from standby mode, a standby recovery management circuit is utilized to minimize WL voltage setup time. The ripple voltage is 3mV at 30pF load with 20MHz pumping frequency in active mode in post-simulation. The WL voltage setup time when recovery from standby mode is equal to 13.7ns, even though the average standby current is less than 0.98µA typically.

9.9 µW, 140 dB DR, and 93.27 dB SNDR, Double Sampling ΔΣ Modulator Using High Swing Inverter-Based Amplifier for Digital Hearing Aids

In this paper, an ultra-low-power second-order, single-bit discrete-time (DT) double sampling ΔΣ modulator was proposed for hearing aid applications. In portable biomedical devices that are permanently used such as hearing aids, short battery lifetime and power dissipation are considerable issues. In a typical delta–sigma modulator, the most power-consuming parts are the operational transconductance amplifiers (OTAs), and their elimination without loss of efficiency is now challenging. This proposed modulator includes an ultra-low-power self-biased inverter-based amplifier with swing enhancement instead of power-hungry OTAs. Low voltage amplifier design reduces output swing voltage, affecting delta–sigma modulator efficiency and decreasing the signal-to-noise and distortion ratio (SNDR) and dynamic range (DR) values. In this article, the proposed amplifier’s source and tail transistors were biased in the sub-threshold region, increasing the output swing voltage significantly and leading to desired properties for a hearing aid modulator. The proposed amplifier peak-to-peak swing voltage was approximately 1.01 V at a 1 V power supply. In addition, the proposed modulator design used a standard 180 nm CMOS technology, which obtained 140 dB DR and 93.27 dB SNDR for a 10 kHz signal bandwidth with an oversampling ratio (OSR) of 128. Finally, the modulator’s effective chip area was 0.02 mm2 and consumed only about 9.9 µW, while the figure of merit (FOMW) and FOMs achieved 1.31 fJ/step and 183.31, respectively.

P‐1.7: Approaching Giga‐Hertz Frequency Characteristic of Low Voltage Organic Field‐Effect Transistor in Subthreshold Region

Low voltage and high frequency organic field‐effect transistors (OFETs) show great potential in the field of wearable devices. To clarify the high frequency operation mechanism of OFETs, this work presents a frequency characterization model and verifies it through simulations in Atlas. The current gain cut‐off frequency model derivation for the OFETs was carried out in the subthreshold region, including conventional physical factors such as effective mobility, channel length, channel width, contact length, and gate dielectric capacitance. Besides these, the trapgap density at the channel was initially considered as an important factor affecting the cut‐off frequency of OFETs. Together with contact lengths, their influence on the current gain cut‐off frequency was verified with simulations in Atlas.

Analytical Physics-Based Modeling of Electron Channel Density in Nanosheet and Nanowire Transistors

We propose a general physics-based approach for an accurate analytical calculation of the channel charge density in field-effect transistors as a function of the external gate biases. This approach is based on consistent consideration of basic electrostatic equation as a balance of electric and chemical potentials which allows us to obtain in a unified way the explicit analytic expressions continuously describing the subthreshold and above threshold regions in the nanosheet (symmetric and asymmetric) and nanowire FETs. Two conceptually different definitions of phenomenological threshold voltage are consistently introduced and discussed.

Analytical drain current model development of twin gate TFET in subthreshold and super threshold regions

In this work, an analytical model for a twin gate Tunnel Field Effect Transistor's drain current operating in the subthreshold and superthreshold regions is proposed. Using this drain current model, the ratio of transconductance to drain current, a crucial metric for the integrated analog circuit design technique, has been retrieved. Due to the simplicity of this approach, it may be quickly implemented for any type of dual gate TFETs by adjusting a few parameters. Comparing the drain current calculated by this analytical model to the drain current simulated by the 2D-Sentaurus TCAD software demonstrates the Tunnel FET's authenticity. The proposed analytical method can be used to achieve the appropriate transconductance for operating Tunnel FETs in the gigahertz region with very low milliwatt power consumption.

On Galvanomagnetic Properties of the 2D Rayleigh Model

periodic arrangement of circular inclusions) with the metal–insulator phase transition are considered. The expression obtained for the corresponding effective conductivity tensor σ^e is valid in the entire subthreshold critical region (up to the contacts of circles) in the vicinity of the transition point. The behavior of components of tensor σ^e in weak and strong magnetic fields is determined.

Cryogenic Characteristics of InGaAs MOSFET

We present an investigation of the temperature dependence of the current characteristic of a long-channel InGaAs quantum well MOSFET. A model is developed, which includes the effects of band tail states, electron concentration-dependent mobility, and interface trap density to accurately explain the measured data over all modes of operation. The increased effect of remote impurity scattering is associated with mobility degradation in the subthreshold region. The device has been characterized down to 13 K, with a minimum inverse subthreshold slope of 8 mV/dec and a maximum ON-state mobility of 6700 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> and with values of 75 mV/dec and 3000 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> at room temperature.

Graphene‐on‐Silicon Hybrid Field‐Effect Transistors

AbstractThe combination of graphene and silicon in hybrid electronic devices has attracted increasing attention over the last decade. Here, a unique technology of graphene‐on‐silicon heterostructures as solution‐gated transistors for bioelectronics applications is presented. The proposed graphene‐on‐silicon field‐effect transistors (GoSFETs) are fabricated by exploiting various conformations of channel doping and dimensions. The fabricated devices demonstrate hybrid behavior with features specific to both graphene and silicon, which are rationalized via a comprehensive physics‐based compact model which is purposely implemented and validated against measured data. The developed theory corroborates that the device hybrid behavior can be explained in terms of two independent silicon and graphene carrier transport channels, which are, however, strongly electrostatically coupled. Although GoSFET transconductance and carrier mobility are found to be lower than in conventional silicon or graphene field‐effect transistors, it is observed that the combination of both materials within the hybrid channel contributes uniquely to the electrical response. Specifically, it is found that the graphene sheet acts as a shield for the silicon channel, giving rise to a nonuniform potential distribution along it, which impacts the transport, especially at the subthreshold region, due to non‐negligible diffusion current.

Highly Sensitive Hybrid Oxide Phototransistors with Photoresponsive Zeolitic‐Imidazolate‐Frameworks for Real‐Time Light Detection

AbstractConventional oxide‐based thin‐film phototransistors (Ph‐TRs) with a hybrid structure with additional photoabsorbers show limitations in real‐time on/off operations without additional input bias. Here, hybrid InGaZnO (IGZO) Ph‐TRs utilizing zeolitic‐imidazolate‐framework‐67 (ZIF‐67), an electrically insulating material with a unique metal‐to‐metal charge transfer (MMCT) pathway enabling charge migration, are presented. A wide photodetection range and fast response/recovery speed without additional gate bias are achieved. In particular, ZIF‐67 used as a photoabsorber exhibits absorption of visible light over a wide range of wavelengths. Photoexcited electrons migrate through the MMCT pathway between Co ions and migrate to the IGZO conduction band, causing a significant change in the photocurrent (Iph) of the hybrid ZIF‐67/IGZO Ph‐TR. In the dark, ZIF‐67 immediately returns to the insulating state, resulting in a fast rise/fall time under dynamic photo‐stimulus. In addition, it exhibits repeatable photo‐sensing performance without persistent photocurrent behavior under pulsed light‐on/off cycles. A high photosensitivity of 108 for red light (592 nm, 0.1 mW cm–2) is obtained as it suppresses the dark current and amplifies photocurrent generation in the subthreshold gate voltage region. This combination of fast response time, high photosensitivity, and high stability is promising for ideal Ph‐TRs, enabling real‐time detection even for high‐frequency operations.

PMOS‐only pW‐power voltage reference with sub‐10 ppm/°C trimmed temperature coefficient and sub‐100 ppm/V line sensitivity

SummaryIn this paper, a new ultra‐low‐power voltage reference based on a two‐stage, all‐pMOS topology operating in the subthreshold region is proposed to uniquely meet the pW‐power range power consumption requirements of emerging Internet‐of‐Things applications without significantly compromising the temperature coefficient (TC) and the line sensitivity (LS) performance. The proposed circuit consists of the LS regulator, TC corrector, and TC trimming sections. Based on post‐layout Monte Carlo simulations in 180‐nm CMOS, the proposed circuit operates with 0.8‐ to 2.4‐V supply potential and generates a reference voltage of 206 mV with a process spread of 7.8%, achieving an average calibrated TC of 4.4 ppm/°C in the temperature range of −20°C to 80°C, and an average LS of 51.5 ppm/V with a power consumption of 25.9 pW at 25°C (469.1 pW at 80°C).

Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node

Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (Isub) and punch-through leakage (IPT) in the sub-channel, is strongly related to the S/D recess process. Firstly, device electrical characteristics such as current density distributions, On/Off-state current (Ion, Ioff), subthreshold swing (SS), RC delay, and gate capacitance (Cgg) are investigated quantitatively for DC/AC performance evaluation and comparison according to S/D lateral recess depth (Lrcs) variations. For both device types, larger Lrcs will result in a shorter effective channel length (Leff), so that the Ion and Ioff simultaneously increase. At the constant Ioff, the Lrcs can be optimized to enhance the device’s drivability by ~3% and improve the device’s RC delay by ~1.5% due to a larger Cgg as a penalty. Secondly, S/D over recess depth (Hrcs) in the vertical direction severely affects the punch-through leakage in the Sub-Fin or bottom parasitic channel region. The NSFET exhibits less Ioff sensitivity provided that it can be well controlled under 12 nm since the bottom parasitic channel is still gated. Furthermore, with both Hrcs and Lrcs accounted for in the device fabrication, the NSFET still shows better control of the off-leakage in the intrinsic and bottom parasitic channel regions and ~37% leakage reduction compared with FinFETs, which would be critical to enable further scaling and the low standby power application. Finally, the S/D recess engineering strategy has been given: a certain lateral recess could be optimized to obtain the best drive current and RC delay, while the vertical over-recess should be in tight management to keep the static power dissipation as low as possible.

Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS

True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. Due to the relatively high leakage currents in modern CMOS processes, the use of leakage protection techniques of the storage nodes in TSPC must be considered, especially at high radiation doses. In this paper, the limitations originating from Total Ionization Dose (TID)-induced subthreshold leakage currents are analysed and radiation-hardening-by-design (RHBD) circuit techniques are proposed. Additionally, Single Event Upsets (SEU) are investigated by quantifying the critical charge of the leakage protected TSPC FF. The results are compared to both the static and the TSPC FF without leakage mitigation.

Investigation and modeling of trap states in ambipolar organic field-effect transistor

This work presents a compact analytical model for charge carrier transport in an ambipolar OFET (a-OFET) based on trap-limited conduction (TLC). The model accounts for tail traps in the band gap of the organic semiconductor (OSC) in order to analyse the transistor behaviour in above threshold regime. For the sub-threshold operation of ambipolar OFET, both deep and interface trap states are accounted for, thus accurately describing the transistor behaviour comprising of drift and diffusion elements respectively. A detailed description of surface potential and field-effect mobility for both the electron and hole carriers, in consequence to these trap states has been presented. Individual current components, obtained as a result of modeling tail, deep and interface trap states are combined using the hyperbolic tangent transition function and are in good agreement with the available experimental data. • This work presents modeling of ambipolar OFET using trap-limited conduction (TLC) approach. • Presented work includes modeling of ambipolar current in both above and below threshold regime, by considering tail, deep and interface acceptor and donor-like states in organic semiconductor. • Subthreshold modeling includes both drift and diffusion components. • Dependence of the mobility of electrons and holes on the characteristic temperatures of the distributions of both tail and deep acceptor and donor-like states has been studied. • The model accurately describes the transfer characteristics of ambipolar OFET.

Subthreshold Delay Variation Model Considering Transitional Region for Input Slew

Subthreshold design provides the promising advantage of low power consumption at the cost of performance variation and even circuit failure. An accurate and efficient statistical timing model is crucial for timing analysis and performance optimization guidance. Prior works lack the consideration of the impact of slew time or the transitional region for input slew due to process variation and efficient approaches considering the impact of load capacitance and multiple process variations in complex gates, resulting in accuracy loss. In this work, an accurate end efficient gate delay variation model is analytically derived for various input slews and load capacitances. The transitional region between fast and slow input slew is efficiently partitioned with an adaptive error tolerance method so as to characterize timing variation by linear interpolation based on that for fast and slow input slew. In order to consider the impact of load capacitance, the relation between the sensitivity of step delay and the dominant threshold voltage variation is analytically derived. For complex gates, the multiple process variations for both parallel and stacking structures are equivalently expressed by threshold voltage variation from each transistor. The proposed model has been validated under advanced TSMC (Taiwan Semiconductor Manufacturing Company) 12 nm technology at subthreshold region and achieves excellent agreement with Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation results with the max error less than 6.49% for standard deviation of gate delay and 4.63%/6.40% for max/min delay, demonstrating over 4 times precision improvement compared with competitive analytical models.

Influence of Bulk Doping and Halos on the TID Response of I/O and Core 150 nm nMOSFETs

The total ionizing dose sensitivity of planar 150 nm CMOS technology is evaluated by measuring the DC responses of nMOSFETs at several irradiation steps up to 125 krad(SiO2). Different TID sensitivities are measured for transistors built with different channel dimensions and operating voltages (I/O and core). The experimental results evidence strong relations between TID sensitivity and the doping profiles in the channel. I/O transistors have the highest TID sensitivity due to their thicker gate oxide and lower bulk doping compared with core devices. In general, narrow-channel devices have the worst degradation with negative threshold voltage shifts, transconductance variations and increased subthreshold leakage currents, suggesting charge trapping in shallow trench isolation (STI). The enhanced TID tolerance of short-channel core devices is most likely related to the increased channel doping induced by the overlapping of halo implantations. Finally, transistors fabricated for low-leakage applications exhibit near insensitivity to TID due to higher bulk doping used during the fabrication to minimize the drain-to-source leakage current.

Critical Assessment of the High Carrier Mobility of Bilayer In2O3/IGZO Transistors and the Underlying Mechanisms

AbstractHigh‐performance bilayer In2O3/IGZO thin‐film transistors (TFTs) fabricated by pulsed laser deposition are reported. The TFTs exhibit an on/off current ratio of 109, a reversed subthreshold slope (ss) of 0.08 V dec−1, and a high saturation mobility of 47.9 cm2 V−1 s−1. The reliability of the mobility values is critically validated and assessed by four‐probe measurements, the transfer‐length method, and the temperature‐dependence. X‐ray photoelectron spectra are combined with C–V measurements to characterize the interface, and the results show that a two‐dimensional electron gas (2DEG)‐like state accumulates at the In2O3/IGZO interface. However, this state only forms in the subthreshold region and does not cause the high carrier mobility in the region above the threshold. Instead, the enhanced carrier mobility results from the intrinsic high mobility of the In2O3, the smooth surface, and the low‐defect states in the In2O3/IGZO bilayer with a good percolation transport path.

MOS only nano-watt sub-bandgap voltage reference

This paper presents a nano-watt bandgap voltage reference (BGR). The self-cascode structure is provided as a proportional-to-absolute-temperature (PTAT) voltage. Due to the low slope of the PTAT voltage, a voltage divider consisting of five similar MOSFET transistors is presented. The resulting output voltage will be one-fifth of the complementary-to-absolute-temperature voltage and four-fifths of the PTAT voltage. All MOSFETs are standard CMOS transistors biased in the sub-threshold region where one of them is utilized as a diode. Post-layout simulation results using the standard 0.18 µm CMOS process show a nominal output voltage of 0.132 V. The power consumption is 12.7 nW at 0.7 V of the power supply. The average temperature coefficient (TC) is about 28.5 ppm/°C over a temperature range of 0 °C–100 °C. The proposed BGR occupies a small area of 0.00083 mm2.

Triple-Node FinFET With Non-Ohmic Schottky Junctions for Synaptic Devices

A triple-node FinFET (TriNo-FinFET) with non-ohmic Schottky junctions is demonstrated for an artificial synapse. The three mechanisms of thermionic emission in a subthreshold region, tunneling in a transition region, and drift transport in an inversion region are utilized in the TriNo-FinFET with non-ohmic Schottky junctions. The transition region dominated by tunneling with non-ohmic Schottky junctions improves the linearity of potentiation and depression. An average recognition rate of 90 % for handwritten digits in the MNIST dataset is achieved. Moreover, the TriNo-FinFET with the double-layered charge trap layer (CTL) shows enhanced weight-update speed by up to 48-fold compared to that with a single-layered CTL.