Subthreshold Region Research Articles

On-chip leakage current variation measurement using external-reference-free current-to-time conversion for densely placed MOSFETs

This paper proposes a time-domain leakage current measurement circuit that uses an external-reference-free current-to-time conversion. Our proposed current-to-time converter (CTC) utilizes a dual inverter-based conversion to provide a stable reference. We share the CTC among the devices under test (DUTs) for accurate characterization of variation. Our CTC, along with a tree-based switch structure, allows us to densely place and route the DUT transistors using a cell-based design flow similar to a digital circuit design. We demonstrate our circuit by measuring subthreshold leakage currents of 256 minimum sized nMOSFETs in a 65 nm bulk low-power CMOS process. We could successfully extract the variations in subthreshold coefficient and subthreshold leakage current at different temperatures. Our circuit is also robust to supply voltage fluctuation making the circuit suitable for accurate characterization of MOSFET parameters for subthreshold operation.

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

This article presents a timing error detection and correction (EDaC) technique optimized for near-/sub-threshold operation to recover energy lost in the conventional signoff margins. The presented EDaC requires no modifications to the processor pipeline and avoids imposing additional hold constraints on monitored paths by instantaneously checking for late activity. Furthermore, two correction methods are discussed: a simple clock gating method and a low cycle overhead clock stretching method. Both provide robust last-minute error prevention. The EDaC is applied in a near-/sub-threshold implementation of the CoolFlux DSP processor and infers only a 2.8% and 2.1% area overhead for the detection and correction, respectively. Silicon measurements validate the EDaC system from 0.25 to 0.7 V (1–200 MHz) and show that it recovers all voltage margins in the near-/sub-threshold region. The design achieves a minimum energy point (MEP) of 8.1 pJ/cycle at 0.34 V and 10 MHz. Here, the EDaC technique reduces the energy consumption by 48%–17.6% with respect to the signoff margins depending on their conservatism, and it enables the processor to operate with only 12% energy overhead compared to its ideal non-margined critical operation point.

Investigation of Hump Behavior of Amorphous Indium-Gallium-Zinc-Oxide Thin-Film Transistor Under Positive Bias Stress

We investigate positive bias stress (PBS)-induced hump behavior in the subthreshold current region of the transfer characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). We analyze the origin of hump creation as parasitic edge conduction using both experiment and simulation. Based on the simulated results, we confirm that an additional narrow (~0.1 eV), Gaussian (~2.94 eV) trap states away from valance band maximum (VBM) is created within the parasitic channel after the PBS. A sharp decrease in the active layer thickness at the edge region of the active layer during the fabrication process increases the electric field during PBS which resulted in the creation of shallow oxygen vacancies at the edge region. As a result, a higher electron concentration at parasitic conduction path turned on the transistor earlier causing hump behavior in the subthreshold region of the transfer curve. Moreover, the increase of various distances between the main channel and the parasitic transistor is also simulated. It is identified that the extended width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W_{E}$ </tex-math></inline-formula> ) of the active layer ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10.5 ~\mu \text{m}$ </tex-math></inline-formula> when compared to the main channel exhibits a significant difference in the conduction current than the parasitic channel and the main channel current is not affected anymore by parasitic conduction which efficiently eliminates the hump.

Effect of Anode Material on the Sensitivity of GaN Schottky Barrier Diode Temperature Sensor

GaN Schottky barrier diode (SBD) temperature sensors with TiN, Ni, and NiN anodes were fabricated in this study to evaluate the effect of anode material and inhomogeneous interface on the sensitivity. The temperature-dependent current–voltage curves negatively shift with the increasing temperature, presenting a slight inhomogeneous barrier behavior. Compared with the Ni anode, the TiN and NiN anodes suppress the inhomogeneity. The sensitivity obtained from the sub-threshold region follows the same tendency for all the SBDs, which increases with the decreasing current level. Furthermore, the NiN anode temperature sensor shows slightly higher sensitivity and better linearity compared with the Ni and TiN anodes, with the highest sensitivity of 2.54 mV/K. The discrepancy between the measured sensitivity and the theoretical value is ascribed to the inhomogeneous interface barrier.

A 1-V 2.69-ppm/°C 0.8-μW bandgap reference with piecewise exponential curvature compensation

This paper presents a low-power precision bandgap reference (BGR) circuit consisting of a current-mode BGR core with piecewise exponential curvature compensation (PECC). Three differential MOS pairs operating in sub-threshold region are combined to generate the piecewise exponential current injecting into the BGR core for curvature compensation, while the voltages with different temperature dependence for three differential pairs are generated in turn from the BGR core. Together with the intrinsic first-order compensation, the proposed scheme actually realizes a 4th-order curvature compensated BGR. The current-mode structure permits the circuit's operation under sub-1V power supply. Fabricated in a 0.18-μm CMOS process, measured results for 88 samples show that the BGR achieves an average temperature coefficient of 2.69 ppm/°C (1.39 ppm/°C–8.6 ppm/°C) in the range of −40 to 125 °C after trimming. The measured line sensitivity is 0.03%/V in the supply range from 1 to 2.5 V. The current consumption is only 0.8 μA under a 1-V supply and the active area is 0.115 mm2.

Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current

The leakage current is prime concern in the modern portable battery operated device. Therefore, various techniques using MOSFET and FinFET devices are presented and their performance is evaluated and compared. To further reduce the leakage current for improved battery backup in portable devices, new devices namely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. The subthreshold leakage power saving is observed in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25 °C) and high temperature (110 °C) with low and high input ranges. For high temperature & high input ranges, the simulation results show power saving from 89.65—97.86% and from 91.85—99.76% when compared with single chiral standard and LECTOR based domino circuits, respectively.

Improved loop stability approach in fully differential operational transconductance amplifier with common‐mode feedback circuit

AbstractThis paper proposes a new approach to improve loop stability in a typical common‐mode feedback (CMFB) circuit of a differential operational transconductance amplifier (OTA). In this paper, a differential difference amplifier (DDA) with a current mirror load is employed as a CMFB circuit. The new approach is based on using two series diode‐connected transistors operating in subthreshold region in parallel with current mirror load. The proposed approach provides a reliable good function with no reduction in the OTA performance and dynamic operation of CMFB loop. The proposed scheme attains necessary high gain and large bandwidth with required phase margin for CMFB circuit. The proposed CMFB circuit is employed in a typical OTA structure. The post‐layout simulation results in TSMC 130‐nm CMOS technology show that the proposed approach leads to a better phase margin of 80°, a high unity gain bandwidth of 800 MHz, and a loop gain of 27 dB for the CMFB circuit.

Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI

In this paper, we present a mixed-signal integrate and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub-threshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30 &#x03BC;<i>m</i>², this is the smallest neuron circuit reported to date.

MIOTA-Based Filters for Noise and Motion Artifact Reductions in Biosignal Acquisition

This paper presents a new low-voltage CMOS structure for operational transconductance amplifier (OTA) exploiting the bulk-driven, the self-cascode and the multiple-input transistor techniques (MI). The multiple-input OTA (MIOTA) circuit operates in subthreshold region using 0.5V supply voltage and offers enhanced linearity. The MIOTA is developed for biopotential signal as well as electrocardiogram (ECG) signal processing circuit and it is exploited to design a 5th-order Chebyshev low-pass and 3rd-order band-pass filters with a dynamic range (DR) of 57.6 dB and 60.4 dB, and nanopower consumption of 50 nW and 60 nW, respectively. Due to the electronic tuning of cut-off frequency, the low-pass and band-pass filters are suitable for random noise and motion artifact noise reductions in biopotential signals. The circuits were designed in Cadence environment using the standard N-well <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> TSMC CMOS technology. Intensive post-layout simulation results along with the process, voltage, temperature analysis (PVT) and Monte Carlo (MC) prove the robustness of the design. The chip area of the proposed MIOTA is 0.00725 mm² (<inline-formula> <tex-math notation="LaTeX">$118~\mu \text{m}\,\,\times 61.5\,\,\mu \text{m}$ </tex-math></inline-formula>). Compared with standard OTA the MIOTA offers simplification of filter topology and reduced number of active elements. In order to demonstrate these advantages, the MIOTA-based filter was also build using commercially available OTA LT1228. The experimental results of OTA LT1228 confirm both the filter functionality and the advantages of the proposed MIOTA.

A Fully MOSFET Voltage Reference with Low Power Consumption and High Power Supply Rejection Ratio for IoT Microsystems

In this work, a fully MOSFET voltage reference (FMVR) circuit with a current consumption of 7.6 nA and a supply voltage of 1 V is proposed. To generate the complementary to absolute temperature (CTAT) voltage, the voltage of a PN junction generated by a PMOS transistor - which is part of the bias circuit - is used. Generation of proportional to absolute temperature (PTAT) voltage is carried-out by utilizing three stages of self-cascode transistors biased in the sub-threshold region. A fraction of the CTAT voltage is added to the PTAT voltage without using an additional circuit to enable acquiring an output reference voltage of about 0.648 V with minimal temperature dependence. The proposed voltage reference is simulated in 0.18 μm of CMOS process and its area occupation is 0.0023 mm2. The obtained post-layout simulation results demonstrate that the proposed FMVR has a temperature coefficient equivalent to 12.9 ppm/°C under the temperature variation from -25 °C to 120 °C. Moreover, the line regulation under supply voltage variation from 0.9 V to 2 V is found to be equal to 0.02 %/V, and a power supply rejection ratio of 44 dB is acquired. Comparing the main parameters of the proposed FMVR - to the state-of-the-art circuits - shows that it has higher efficiency with smaller area and lower power consumption.

Subthreshold modeling of ambipolar organic field-effect transistor based on field-dependent mobility

In the present work, an ambipolar charge transport model based on the field dependent mobility is presented for the electron accumulation mode. The model is derived using the charge drift approach, which is later extended to include subthreshold ambipolar region, using an asymptotically interpolation function. A methodology for the extraction of model parameters is discussed. The extracted parameters are then used to obtain the field dependent mobility for both holes and electrons. The role of traps in modulating the electron and hole mobility as a function of gate voltage is presented. It is demonstrated that the output and transfer characteristics obtained from the model are in close proximity with the experimental results presented by of Zhang et al. (2017).

Design of half adder using integrated leakage power reduction techniques

The necessity for the development of compact, portable, and reliable electronic devices of enhanced speed and efficiency has prompted the scaling of CMOS devices to be indispensable. However, the benefit of scaling CMOS devices comes at the cost of increased leakage current in circuits. The variance in power consumption by these circuits incites detrimental impacts on the operational characteristics of the entire device. So, in this work, a novel leakage power reduction technique obtained by combining the Leakage Control Transistor (LECTOR) approach and drain gating approach is proposed. Both these subthreshold leakage minimization approaches are prominently used in Complementary Metal Oxide Semiconductor (CMOS) devices for curtailing the leakage power. The effectiveness of the proposed Integrated Drain Gating Lector (IDGL) technique in mitigating the leakage power is ascertained by designing a half adder circuit. Hence the overall leakage power is of 3.16nW & delay 69.12 µs in 180 nm technology, and in low scale technology of 90 nm the same leakage power decline to 2.19nW & delay is 65.45 µs.

A 3T eDRAM In-Memory Physically Unclonable Function With Spatial Majority Voting Stabilization

This letter presents a 3T eDRAM in-memory physically unclonable function (PUF) for low-cost Internet of Things (IoT) applications. The proposed design integrates PUF to eDRAM with a small peripheral overhead. With the subthreshold leakage of the bit-cell read path exploited as the entropy source, two adjacent 3T eDRAMs (with 2 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 197 F²&#x003D;394 F² area) race to generate the key bit. To overcome voltage and temperature variations, the spatial majority voting (SMV) is adopted. Implemented in 65-nm CMOS, the proposed eDRAM PUF achieves &#x003C; 0.35&#x0025; bit error rate (BER) across a voltage range of 1.0&#x2013;1.2 V and temperature range of 0 &#x00B0;C&#x2013;60 &#x00B0;C, presenting a low-cost and robust solution for IoT security.

Characterization and Modeling of Quantum Dot Behavior in FDSOI Devices

A compact analytical model is proposed along with a parameter extraction methodology to accurately capture the steady-state (DC) sequential tunnelling current observed in the subthreshold region of the transfer IDS-VGS characteristics of MOSFETs at cryogenic temperatures. The model is shown to match measurements of p-MOSFETs and n-MOSFETs manufactured in a commercial 22nm FDSOI foundry technology, with reasonable accuracy across bias conditions and temperature (2 K -50 K). Furthermore, the extracted model parameters are used to analyze the impact of the gate and drain voltages and of layout geometry on the device characteristics.

A Robust Area-Efficient Physically Unclonable Function With High Machine Learning Attack Resilience in 28-nm CMOS

Strong physically unclonable function (PUF) offers a promising solution to low-cost hardware identification and authentication for Internet of Things (IoT) applications. The continuous advancement of machine learning (ML) technology makes the PUF resilience to ML attacks a major design priority. This paper presents a robust and area-efficient strong PUF design with high ML attack resilience. The proposed PUF architecture based on inverter amplifiers operating in the subthreshold region achieves both low energy consumption and high supply and temperature scalability. The proposed nonlinearity topology effectively enhances PUF resilience to various ML attacks with low implementation area and cost. The proposed strong PUF design was designed and implemented using a 28-nm CMOS process. The measurement results show that the proposed PUF design achieves a nearly ideal ML attack resilience of 49.96 &#x0025; with a small area of 239,857 F², and demonstrates a stable operation across a wide range of supply voltage from 0.5&#x2013;1.4 V and temperature from &#x2212;40&#x2013;100 &#x00B0;C. This represents <inline-formula> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> improvement in area efficiency, <inline-formula> <tex-math notation="LaTeX">$2.25\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$1.08\times $ </tex-math></inline-formula> improvement in operating voltage and temperature range, respectively, compared to the state-of-the-art results.

Physical based compact model of Y-Flash memristor for neuromorphic computation

Y-Flash memristors utilize the mature technology of single polysilicon floating gate nonvolatile memories. It can be operated in a two-terminal configuration similar to the other emerging memristive devices, e.g., resistive random-access memory and phase-change memory. Fabricated in production complementary metal-oxide-semiconductor technology, Y-Flash memristors allow excellent reproducibility reflected in high neuromorphic products yields. Working in the subthreshold region, the device can be programmed to a large number of fine-tuned intermediate states in an analog fashion and allows low readout currents (1 nA ∼ 5 μA). However, currently, there are no accurate models to describe the dynamic switching in this type of memristive device and account for multiple operational configurations. In this paper, we provide a physical-based compact model that describes Y-Flash memristor performance in both DC and AC regimes and consistently describes the dynamic program and erase operations. The model is integrated into the commercial circuit design tools and is ready to be used in applications related to neuromorphic computation.

Influences of vacuum annealing induced oxygen defects on the transfer characteristics of a-ITO thin-film transistors

Amorphous indium–tin-oxide (a-ITO) films are fabricated by pulsed laser deposition at room temperature and annealed in vacuum. Although vacuum annealing could ameliorate the carrier mobility and subthreshold swing, the threshold voltage shows a negative shift upon vacuum annealing at 450 K, and a hump emerges in the subthreshold region. The density of electronic states extracted by Grünewald method demonstrate that the hump is caused by shallow donor-like states. Furthermore, the X-ray photoelectron spectra and the photoconductivity experiment reveal that the shallow donors are ascribed to the increased oxygen defects upon thermal annealing.

A comprehensive analytical model for ambipolar transport in nano-dimensional VOPc/p-6P OHJFET for applications in organic electronics

This paper presents a compact analytical DC model for high mobility VOPc (vanadyl pthalocyanine)/p-6P (para-sexiphenyl) ambipolar organic heterojunction field-effect transistor (OHJFET). The proposed model accounts for both unipolar and ambipolar regimes of VOPc/p-6P ambipolar OHJFET by considering spatial charge carrier density in the channel. The model incorporates subthreshold conduction phenomenon in addition to describing beyond threshold transport. The model is extended to describe ambipolar regime occurring in subthreshold region at low drain to source voltage, V DS. Device characteristics and various parameters obtained are presented and are further used to model recombination zone and channel potential profile. Results obtained, are compared with available experimental data and a good match is observed.

Reliability analysis of cost-efficient CH3NH3PbI3 based dopingless tunnel FET

Electrostatically-doped TFETs (ED-TFETs) are amongst the most widely used cost-efficient steeper devices due to the use of charge-plasma technique and tunneling mechanism. However, the reliability analysis of ED-TFETs is considered an important concern for the research community. Most studies have only focused on improving the performance of ED-TFETs such as dopingless (DL)-TFET in terms of on-current (I ON), subthreshold swing (SS) and threshold voltage (V th), rather than investigating the reliability issues. In this context, the aim of our work is to investigate the reliability analysis of our previously reported methyl-ammonium lead tri-iodide materials based DL-TFET (MAPbI3-DL-TFET). The influence of interface trap charges, shallow and deep defects on the electrical and analog performance of MAPbI3-DL-TFET has been analyzed using the Silvaco ATLAS tool at room temperature. Extensive results produced show that deep-level (Gaussian) defects impact the performance of the device prominently while the tail defects affect the device performance insignificantly. The present findings showed that the donor/acceptor trap charges impact the device in the subthreshold region considerably, while in the superthreshold region the impact of trap charges is marginal. In our view, these results emphasize the reliability analysis of MAPbI3-DL-TFET for the very first time. We hope that our research will be useful and valuable for DL-TFET manufacturers.

Graphene/MoS₂ Thin Film Based Two Dimensional Barristors With Tunable Schottky Barrier for Sensing Applications

In this work, a large-area MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /graphene barristor device, with an electrically tunable Schottky barrier height, has been studied for detection of various gaseous analytes. The Schottky barrier height could be modulated by over 0.65 eV, allowing the drain current to be tuned by many orders of magnitude. Using diluted NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gases as analytes, the performance of the barristor device was compared with individual MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and graphene based planar FETs, where the barristor device outperformed its counterparts in terms of response magnitude and limit of detection. Due to the atomically thin nature of MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and graphene, electric field applied to one material could not be fully screened from the other one, which allowed both materials to act as a composite structure when analyte molecules interacted with the barristor device. This apparently reversed the dopant behavior of NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , while increasing the device sensitivity through subthreshold operation. Both conductance and capacitance based measurements are presented to highlight the charge transfer and barrier height modulation, to support the unique sensing mechanism observed in the 2D barristor device. A lower limit of detection in low ppb is established for NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and low ppm for NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , which could be further tuned by altering gate-drain bias conditions.