Sub-sampling PLL Research Articles

Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur

Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur

A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression

This article presents a 2-GHz dual-path subsampling phase-locked loop (SSPLL) with ring voltage-controlled oscillator (VCO) phase noise suppression (PNS). In addition to the conventional subsampling charge pump (SSCP), a high-pass path from the subsampling phase detector (SSPD) to the low-pass filter (LPF) is implemented in the proposed SSPLL. Due to this dual-path architecture, a new in-band zero and pole are introduced into the open-loop transfer function (zero frequency is smaller than the pole frequency), which extends the open-loop unit-gain bandwidth without sacrificing the phase margin. Consequently, the phase noise contribution of the ring VCO is suppressed while the loop stability is ensured. Meanwhile, the phase noise contribution of the high-pass path is negligible compared to the reference and ring VCO’s contribution. Measurement results show that the SSPLL’s closed-loop bandwidth is extended to around 6 MHz with a reference of 20 MHz and the jitter is reduced by 1.34 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> (from 3.52 to 2.63 ps) with a maximum noise suppression of 6.5 dB at the 1.1-MHz offset. The PNS path consumes 0.16 mW and no delay line or calibration is needed, which results in a relatively high FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{PNC}}$</tex-math> </inline-formula> value of 40.5 dB.

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment

A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC

A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).

A Highly Accurate and Sensitive mmWave Displacement-Sensing Doppler Radar With a Quadrature-Less Edge-Driven Phase Demodulator

A 110-mW 39-GHz Doppler radar front end in 65-nm CMOS for displacement and vibration sensing is proposed. Conventional Doppler radar suffers from detection nulls, at which the receiver detection gain drops to zero. Quadrature demodulation for either carrier frequency or intermediate frequency (IF) is necessary to alleviate nulls but still induces nonlinear detection gain that needs to be compensated through digital signal processing (DSP). In this article, a Doppler radar topology is proposed to achieve ultrahigh displacement range accuracy and sensitivity and to eliminate detection nulls without using quadrature demodulation. An edge-driven phase demodulator (EDPD) processes the rectified square-wave intermediate signal and converts displacement/vibration to a true-dc/baseband signal with a constant gain. Coherent demodulation and signal generation through common-referenced subsampling phase-locked loops (SSPLLs) allow the radar to achieve 4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m static range accuracy and 39-nm vibrational (at 10 kHz) range sensitivity in measurement.

A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a −70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL

This paper investigates the mechanisms of spurious contents in a ring-VCO-based sub-sampling phase-locked-loop (SSPLL). An area-efficient solution to suppress reference spurs in a ring-VCO-based SSPLL is proposed using an auxiliary capacitor-multiplier-based delay-locked loop (DLL). Besides, the implementation of a finite state machine circuit with a narrow dead zone improves the relocking time and reduces the power consumption of the PLL. Implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m CMOS technology, the SSPLL has an active area of 0.051 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , while consuming a dc power of 4.89 mW at an output frequency of 2.4 GHz. Based on measurement results, the proposed circuit achieves an in-band phase noise of -107 dBc/Hz at 1-MHz offset and a reference spur of -70 dBc. The integrated RMS jitter from 1-kHz to 10-MHz interval is 877.5 fs.

GalEPR: A Galvanically Coupled Electron Paramagnetic Resonance Spectrometer for Deep Tissue Hypoxia Diagnosis

This work presents a galvanically coupled electron paramagnetic resonance spectrometer (GalEPR) for deep tissue oximetry and hypoxia diagnosis. Current in vivo EPR spectroscopy directly trades between the operation frequency (equivalent to sensitivity) and the penetration depth due to tissue absorption. Prior art is limited to 1.2 GHz/15 mm and 9 GHz/2 mm. To address this issue, a 30-MHz clock is galvanically coupled through the body to minimize attenuation and up-converted to 14 GHz by a low-power subsampling phase locked loop (SSPLL). The EPR spectrum is measured by an ultrasensitive low-power inductor sensor. The proposed GalEPR spectrometer demonstrates 14 GHz/50 mm frequency/depth (10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> better) with an in vitro hypoxia detection experiment.

Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems

This paper compares four phase-locked loops (PLLs) for mobile audio applications. We compare and analyze PLL structures and discuss the optimized PLL structure in the audio band frequency. A charge-pump-based integer-N PLL (NPLL) is employed as a reference. To improve the jitter performances, multiplying delay-locked loop (MDLL), sub-sampling PLL (SSPLL), and reference-sampling PLL (RSPLL) are employed and analyzed. The frequency range of the PLLs is from 8 MHz to 71.5 MHz. These PLL chips are fabricated using a Samsung 0.13-μm CMOS process. The resulting figures-of-merit for the NPLL, MDLL, SSPLL, and RSPLL are -204.3, -211.07, -220.29, and -213.32 dB, respectively, at 24.576 MHz. The total power consumption from a 1.5-V supply voltage is 1.82, 1.35, 1.43, and 1.64 mW, respectively.

A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier

This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> , FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and total power consumption are −245.1, −260.1 dB, and 9.85 mW, respectively.

A 2.4-GHz Sub-Sampling PLL With an Adaptive and No Power Contribution FLL Achieving 103.58 fs rms Jitter and −257.8 dB FOM

A sub-sampling PLL (SSPLL) employing an adaptive frequency-locked loop (FLL) without static power consumption is proposed in this letter. A new unlock detection mechanism and a configurable PFD are realized in the adaptive FLL. With the new unlock detection mechanism, while the FLL that contains phase detector, divider, and charge pump dissipates no power during the locked steady state, it automatically starts when external interferences disturb the locked state. The optimized dead zone in the configurable PFD ensures a rapid relocking operation. Based on the proposed adaptive FLL, the 2.4 GHz SSPLL is fabricated in a 40-nm CMOS process. It achieves &#x2212;128.5 dBc/Hz at 1 MHz offset frequency and the rms jitter is 103.58 fs integrated from 10 k to 10 MHz. It consumes 1.55 mW at 1 V supply and achieves &#x2212;257.8 dB FOM.

A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop

This article presents a wide-lock-in-range and ultralow-jitter, 12-14.5 GHz subsampling phase-locked loop (SSPLL) using a frequency-disturbance-detecting/correcting (FDC) loop. By detecting and correcting the frequency disturbance, ${f_{{D}}}$ , frequently, the FDC loop can increase the lock-in range of the SSPLL to 3.2 times the reference frequency, ${f_{{REF}}}$ . Since the FDC loop only is concerned with correcting an ${f_{{D}}}$ -event at the output and is not concerned with the jitter, there is no design tradeoff between the jitter, and the power consumption as is the case in previous techniques. Due to its logic using frequency information rather than phase, the FDC loop also can reduce the time required for the reacquisition of the frequency. In this work, the prototype SSPLL was fabricated in a 65 nm CMOS, and it used the 50 MHz ${f_{{REF}}}$ . In the measurements, the FDC loop that consumed only 150 μW of power made the SSPLL achieve the lock-in range of 160 MHz and the frequency-reacquisition time of less than 800 ns. The measured rms jitter at 13 GHz was 83 fs. The active area was 0.23 mm², and the total power consumption was 7.7 mW.

A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL

A sub-sampling phase-locked loop (SSPLL) with a sub-sampling delay-locked loop is presented to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop is added to align the falling edge of the reference clock with the rising one of the output clock. The proposed SSPLL is realized in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18 {\mu }\text{m}$ </tex-math></inline-formula> CMOS process and its active area is 0.185mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . At the output frequency of 2.2GHz, the proposed SSPLL achieves an in-band phase noise of −111.83dBc/Hz and −116.41dBc/Hz at 100kHz and 4MHz offset frequency respectively with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 655fs. The measured reference spur is −50.3dBc.

A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched Gm for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs

A technique to reduce the area of a low-noise sub-sampling PLL (SSPLL) is proposed. The resistor in the loop filter is eliminated. The transconductor driven by the phase detector is switched such that its output consists of a positive and negative pulse with the former wider than the latter. A low frequency zero can thus be realized with a substantially smaller capacitor. Transconductor noise is suppressed to acceptable levels by the high phase-detector gain. In applications that require low out-of-band phase noise, the capacitance can be reduced by <inline-formula> <tex-math notation="LaTeX">$25\times $ </tex-math></inline-formula> or more with typical PLL parameters. A prototype SSPLL from 24.4GHz&#x2013;29.2GHz with a 50MHz reference clock and bandwidth of 1MHz in 65nm LP CMOS process uses a loop filter capacitance of only 5pF. The conventional topology would require 38pF for the same integrated jitter. The in-band phase noise at 1MHz offset ranges from &#x2212;90 to &#x2212;95dBc/Hz, and the out-of-band phase noise at 10MHz offset ranges from &#x2212;117 to &#x2212;121 dBc/Hz. The jitter integrated from 10kHz to 50MHz is 330&#x2013;390 fs. It consumes 18.2mW, exhibiting a minimum FoM of 235dB over the frequency range. The SSPLL occupies an area of only 0.14mm².

A 0.8 V, 5.3-5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and -251.6 dB FoM.

This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and dB FoM.

Photonic microwave synthesizer based on optically referenced sub-sampling phase-locked optoelectronic oscillator

Wideband and low phase noise microwave synthesizers are of critical significance for various applications. Phase-locked loop (PLL) based microwave synthesizers are widely used. Normally, the phase noise of the PLL based microwave synthesizer is limited by the phase noise of the reference, phase detector, frequency divider and voltage-controlled oscillator (VCO). It is challenging to achieve a pure electronic microwave synthesizer with wide frequency coverage and low phase noise, simultaneously. Here, we propose a photonic microwave synthesizer which incorporates an ultra-low phase noise fiber mode-locked laser (MLL) based reference and a wideband frequency tunable optoelectronic oscillator (OEO) based VCO in a hybrid optoelectronic sub-sampling PLL. The frequency of the OEO can be locked to the harmonics of the repetition-rate of the fiber MLL, which combines the distinct advantages of the low phase noise of MLL and the wideband frequency tuning of OEO. A sub-sampling phase detector formed by a balanced optical microwave phase detector (BOMPD) eliminates the use of RF frequency divider and maintains low residual phase noise. We attain an X- and Ku-band photonic microwave synthesizer with over an octave frequency coverage from 8 GHz to 18 GHz, frequency synthesis step of 60.74 MHz and phase noise of -80 dBc/Hz at 100 Hz offset and -100 dBc/Hz at 1 kHz offset for 10 GHz output. The characteristics of the optoelectronic sub-sampling phase detector, the phase-locking dynamics of the hybrid optoelectronic PLL, and the phase noise of the synthesized RF signals are both theoretically and experimentally investigated. The experimental results agree well with the theoretical models. Our approach is promising to achieve wideband and low phase noise microwave synthesis.

A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer

A three-stage low phase noise cascaded phase locked loop (PLL) with reference quadrupler and phase-interpolated (PI) frequency divider is presented in this paper. The first stage consists of a frequency doubler and an injection locked (IL) loop. By increasing the reference frequency from 50 MHz to 200 MHz, the maximum loop division ratio is deduced, yielding to 12 dB in-band noise transfer gain suppression and larger loop bandwidth. The second stage is a fractional-N PLL. In order to mitigating the effect of quantization noise in fractional-N model, a double-orthogonal PI frequency divider is utilized. The division ratio step is reduced from 1 to 1/32, leading to 30 dB quantization noise suppression. The third stage is a hybrid charge-pump (CP) and sub-sampling PLL (SSPLL). By utilizing this hybrid structure, the third-stage output phase noise is dominated by the output clock of the second stage. The PLL is designed and simulated in 65 nm CMOS process. At 2.4 GHz, the spot phase noise are −100 and −114 dBc/Hz at 10 kHz and 1 MHz offsets respectively and the power consumption is 12 mW.

A Charge Pump Current Mismatch Compensation Design for Sub-Sampling PLL

A current mismatch compensation structure for SSPLL charge pump (CP) is proposed and implemented in a low-power 40.5GHz frequency synthesizer. Transistor's channel-length-modulation (CLM) effect induces SSPLL loop gain distortion and decreases VCO control voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ctrl</sub> ) locking range (LR). The proposed compensated CP uses feedback loops to cancel the CLM effect and hence extends V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ctrl</sub> LR from 0.50V to 0.75V under a 1V supply, without degrading SSPLL noise performance. As a result of the more efficient use of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ctrl</sub> range, VCO capacitor bank setup number is reduced from 10 to 7 to cover the same 10% total tuning range. Due to the low-power dividerless structure with sub-sampling lock detector (SSLD) for frequency acquisition, the SSPLL with the proposed compensated CP consumes only 9.5mW power with 192fs RMS jitter.

A Cascaded Mode-Switching Sub-Sampling PLL With Quadrature Dual-Mode Voltage Waveform-Shaping Oscillator

A cascaded mode-switching sub-sampling PLL with quadrature dual-mode voltage waveform-shaping oscillator is proposed in this paper. The dual-mode voltage waveform-shaping oscillator is introduced to extend the tuning range and improve phase noise performance at mm-wave frequency, simultaneously. Meanwhile, the dual-mode quadrature topology is investigated to reduce the phase noise and quadrature phase error, compared to conventional quadrature oscillator. Then, the proposed oscillator is applied in a cascaded PLL with divider-less mode-switching sub-sampling loop, which can obtain the merits of high frequency-resolution, low loop noise, and wide frequency locking range. Both the dual-mode voltage waveform-shaping oscillator and the cascaded PLL are verified and fabricated in a 28-nm CMOS process. The FoM and FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of the oscillator at 10 MHz offset are -188.2 dBc/Hz and -200.7 dBc/Hz respectively. The proposed PLL prototype exhibits a frequency range from 22.8 to 33.9 GHz with a typical power consumption of 41.7 mW. The phase noise across the frequency band is from -104.1 to -108.2 dBc/Hz at 1 MHz offset. The jitter FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</sub> is -236.2 dB.

Low-Power and Low-Noise Millimeter-Wave SSPLL With Subsampling Lock Detector for Automatic Dividerless Frequency Acquisition

An 8.8-mW, low-noise, 40.5-GHz frequency synthesizer is proposed. The synthesizer system consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a 900-MHz high-frequency-reference (HFR) PLL, and a novel subsampling lock detector (SSLD). The SSLD keeps monitoring the locking status of the SSPLL by sampling the SSPLL output with the HFR 900-MHz reference and automatically controls the SSPLL for frequency acquisition if it loses lock or locks to a wrong 100-MHz harmonic. This is done without using a power-consuming divider-based frequency-locked loop in conventional SSPLL. Due to the relatively low-frequency operation and moderate noise requirement of HFR, as well as the low-power SSLD, the proposed system achieves low power consumption and jitter simultaneously. The measured results show 8.8-mW power consumption and 228-fs rms jitter with in-band and out-band phase noises of -96.6 dBc/Hz at a 1-MHz offset and -106.9 dBc/Hz at a 10-MHz offset, respectively.