A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a −70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL

Abstract

This paper investigates the mechanisms of spurious contents in a ring-VCO-based sub-sampling phase-locked-loop (SSPLL). An area-efficient solution to suppress reference spurs in a ring-VCO-based SSPLL is proposed using an auxiliary capacitor-multiplier-based delay-locked loop (DLL). Besides, the implementation of a finite state machine circuit with a narrow dead zone improves the relocking time and reduces the power consumption of the PLL. Implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m CMOS technology, the SSPLL has an active area of 0.051 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , while consuming a dc power of 4.89 mW at an output frequency of 2.4 GHz. Based on measurement results, the proposed circuit achieves an in-band phase noise of -107 dBc/Hz at 1-MHz offset and a reference spur of -70 dBc. The integrated RMS jitter from 1-kHz to 10-MHz interval is 877.5 fs.