A Sub-Sampling Phase-Locked Loop With a Robust Agile-Locking Frequency-Locked Loop

Abstract

This paper presents a sub-sampling phase-locked loop (SSPLL) with the proposed digital counter-based frequency-locked loop (FLL) to achieve agile and robust frequency locking. With a 20-MHz reference frequency, the measured SSPLL in-band phase noise at 2.42 GHz is −110 dBc/Hz; the reference spur is −50 dBc. Fabricated in a 90-nm CMOS and operated from a 1.2-V supply, the SSPLL including the proposed FLL consumes 14.5 mW while the power consumption is reduced to 3 mW when the FLL is turned off. Under a 500-mV VCO supply perturbation, the SSPLL returns to its stable locked frequency in about <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5\ \mu\text{sec}$</tex> .