Abstract
This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and dB FoM.
Highlights
Since 1969, the LC-based phase-locked loops (PLLs) have been developed for over fifty years [1]
In a classical charge pump PLL (CPPLL) system [9,10,11,12,13,14,15], phase noise is mainly generated from two parts: out-of-band noise which is dominated by the voltage-controlled oscillator (VCO); and in-band noise which is dominated by the phase detector, charge pump and divider
The proposed low-voltage hybrid dual-path sub-sampling phase-locked loop (SSPLL) is fabricated in 40-nm CMOS technology
Summary
Since 1969, the LC-based phase-locked loops (PLLs) have been developed for over fifty years [1]. Several designs of LC-based PLLs are reported recently to save power consumption [2,3,4,5,6,7,8] as urgent demands of low power requirements for integrated circuits (ICs) appear. Decreasing supply voltage is an effective way to achieve low power. Improving the noise feature with lower supply voltage is very attractive. Several efforts have been addressed to study the phase noise of VCOs [16,17,18] and designs with ultra-low power consumption have been published [19,20,21]. This paper concentrates on the improvement of in-band noise at low supply voltage
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