Stuck-at Faults Research Articles

On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits

We demonstrate that undetectable single stuck-at faults in full-scan benchmark circuits tend to cluster in certain areas. This implies that certain areas may remain uncovered by a test set for single stuck-at faults. We describe an extension to the set of target faults aimed at providing a better coverage of the circuit in the presence of undetectable single stuck-at faults. The extended set of target faults consists of double stuck-at faults that include an undetectable fault as one of their components. The other component is a detectable fault adjacent to the undetectable fault. We present experimental results of fault simulation and test generation for the extended set of target faults.

Test pattern generation for droop faults

In nanometer ICs, when several transistors in physical proximity switch within the same clock cycle, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. Transistors may slow down because of lower supply voltage. Modelling of such timing faults, termed as droop faults, and their impact on the functionality and timing behaviour of the circuit are yet to be fully understood. In this study, a simple automatic test pattern generation (ATPG) based procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits and full scan sequential circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 and ISCAS-89 benchmark circuits reveal that a very high droop fault coverage can be obtained by applying a short sequence of test vectors.

Formal Reliability Analysis Using Theorem Proving

Reliability analysis has become a tool of fundamental importance to virtually all electrical and computer engineers because of the extensive usage of hardware systems in safety and mission critical domains, such as medicine, military, and transportation. Due to the strong relationship between reliability theory and probabilistic notions, computer simulation techniques have been traditionally used to perform reliability analysis. However, simulation provides less accurate results and cannot handle large-scale systems due to its enormous CPU time requirements. To ensure accurate and complete reliability analysis and thus more reliable hardware designs, we propose to conduct a formal reliability analysis of systems within the sound core of a higher order logic theorem prover (HOL). In this paper, we present the higher order logic formalization of some fundamental reliability theory concepts, which can be built upon to precisely analyze the reliability of various engineering systems. The proposed approach and formalization is then utilized to analyze the repairability conditions for a reconfigurable memory array in the presence of stuck-at and coupling faults.

Guest Editors' Introduction: Special Section on System-Level Design of Reliable Architectures

Guest Editors' Introduction: Special Section on System-Level Design of Reliable Architectures

On ATPG for Multiple Aggressor Crosstalk Faults

Crosstalk faults have emerged as a significant mechanism of circuit failure due to decreasing process geometries and increasing operation frequencies. Long signal nets are highly susceptible to crosstalk faults because they tend to have a higher coupling capacitance to overall capacitance ratio. Moreover, a typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk induced delay on a victim net, it may be impossible to activate all aggressors logically or simultaneously to constructively induce maximum noise at the victim. Therefore, pattern generation must focus on activating a maximal subset of aggressors, weighted by actual coupling capacitance value, in close temporal proximity of the victim net transition. This max-satisfiability problem is constrained by fault effect propagation condition which involves determining an input signal assignment so as to propagate the fault effect at the victim to the primary output. In this paper, we present Automatic Test Pattern Generation (ATPG) solutions for multiple aggressor crosstalk faults for zero and unit delay models and compare the magnitude of crosstalk induced delay at the victim net. Our solution involves a combination of 0-1 Integer Linear Programming (ILP), for maximal aggressor excitation. Fault effect propagation is solved independently by using traditional stuck-at fault ATPG or by generating additional ILP constraints thus forming a integrated ILP formulation with error propagation. The effect of gate delays is summed by circuit transformation. The proposed technique was applied to ISCAS85 benchmark circuits. Results indicate that the percentage of total capacitance that can be switched varies from 75-100% for zero delay and 30-80% for variable delay case while achieving propagation of the fault effect to primary output.

Initialization-Based Test Pattern Generation for Asynchronous Circuits

A novel test pattern generation method for asynchronous circuits is described and evaluated in detail. The method combines conventional pattern generation with hazard-free state initialization. Any type of asynchronous circuit can be processed, and all stuck-at faults, even those inside state-holding elements, such as C-elements, are considered. The results on some of the largest benchmarks ever used for asynchronous circuit testing show fault coverage on the order of 99% with no area overhead for (quasi-)delay-insensitive datapath circuits.

Analysis of multibackground memory testing techniques

Analysis of multibackground memory testing techniquesMarch tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions which we can change is the initial memory background. In this paper we compare the efficiency of multibackground tests based on four different algorithms of background generation.

Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques

This work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests of similar coverage but with fewer specified bits. The second technique is dynamic; it generates a test set from a zero base using a hierarchical fault-compatibility algorithm. Both methods are applicable to any enumerative fault method (linear to the circuit size). The experiments performed using the stuck-at fault model demonstrate the superiority of the proposed methods over comparable existing techniques, in reducing the total number of specified bits per generated test set. The applicability of the generated relaxed test sets is demonstrated for one, out of the many, possible applications, that of deterministic test set embedding. A general framework that integrates the proposed relaxation methods in two popular LFSR-based test set embedding schemes (full and partial reseeding), along with a systematic exploration of related parameters, is proposed. The obtained results show significant reductions in seed storage requirements.

Diagnosis of path delay faults based on low-coverage tests

Fault diagnosis processes consider the fact that a circuit fails a test as carrying more information than if the circuit passes a test. As a result, tests that detect smaller numbers of faults are likely to result in more accurate fault diagnosis. We study the existence of low-coverage tests, which detect small numbers of faults, for stuck-at faults, transition faults and path delay faults. The study shows that such tests are prevalent for path delay faults. We discuss the use of low-coverage tests for diagnosis of path delay faults, and describe a procedure for generating low-coverage tests for path delay faults.

TOV: Sequential Test Generation by Ordering of Test Vectors

We describe a new approach to test generation for stuck-at faults in synchronous sequential circuits. Under this approach, the input vectors comprising the test sequence are fixed in advance. The process of generating the test sequence consists of ordering the precomputed input vectors such that the resulting test sequence has as high a fault coverage as possible. The advantage of this approach is that its computational complexity is limited by limiting the search space to a given set of input vectors and a given test sequence length. We describe a specific implementation of this approach. Experimental results demonstrate that restricting the search space to a fixed number of precomputed input vectors is sufficient for achieving the highest known fault coverage, or a fault coverage close to it, for benchmark circuits.

Dynamic Model-Based Fault Tolerant Control of Variable Air Volume Air Conditioning System

A dynamic model-based fault tolerant control of a variable air volume air conditioning system is developed. State space model of the variable air volume air conditioning system is used to detect, isolate, and estimate stuck faults of the damper vanes of the air handling unit (AHU). Fault identification is implemented by an adaptive interactive multiple observer scheme. It has been shown analytically that observers representing faults in two mutually redundant variable air volume flow control boxes wrongly converge to the same value even when fault has occurred in only one variable air volume flow control box. An input modification scheme is proposed to prevent convergence of the observer corresponding to the functional variable air volume box. Using the information regarding the fault, its effect is minimized. This is achieved by applying the control distribution concept.

Fault Detection Multipliers in Polynomial and Normal Basis

With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults especially in sensitive and critical applications may cause serious failures and hence should be avoided. In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. New architectures are developed to detect erroneous outputs caused by certain types of faults in bit-serial polynomial basis multipliers and digit-serial normal basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults. The full text of the article is not available in the cache. Kindly refer the IJCA digital library at www.ijcaonline.org for the complete article. In case, you face problems while downloading the full-text, please send a mail to editor at editor@ijcaonline.org

Autonomic fault-handling and refurbishment using throughput-driven assessment

An evolvable hardware paradigm for autonomic regeneration called Competitive Runtime Reconfiguration ( CRR) is developed whereby an individual's performance is assessed using the dynamic properties of the population rather than a static fitness function. CRR employs a Sliding Evaluation Window of recent throughput data and a periodically updated Outlier Threshold which avoids the extensive downtime associated with exhaustive Genetic Algorithm (GA) based evaluation. The relative fitness measure favors graceful degradation by leveraging the behavioral diversity among the individuals in the population. Throughput-driven assessment identifies configurations whose discrepancy values violate the Outlier Threshold and are thus selected for modification using Genetic Operators. Application of CRR to FPGA-based logic circuits demonstrates the identification of configurations impacted by a set of randomly injected stuck-at faults. Furthermore, regeneration of functionality can be observed within a few hundred repair iterations. The viable throughput of the CRR system during the repair process was maintained at greater than 91.7% of the fault-free throughput rate under a number of circuit scenarios. CRR results are also compared with alternative soft computing approaches for autonomous refurbishment using the MCNC-91 benchmarks.

RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences

Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. However, they suffer from low defect coverage since they are mostly derived in practice from existing design-verification test sequences. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a DFT method that uses the register-transfer level (RTL) output deviations metric to select observation points for an RTL design and a given functional test sequence. Simulation results for six ITC?99 circuits show that the proposed method outperforms two baseline methods for several gate-level coverage metrics, including stuck-at, transition, bridging, and gate-equivalent fault coverage. Moreover, by inserting a small subset of all possible observation points using the proposed method, significant fault coverage increase is obtained for all benchmark circuits.

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.

A Low Overhead High Test Compression Technique Using Pattern Clustering With $n$-Detection Test Support

This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. The test data to be stored in the automatic test equipment (ATE) memory are much smaller than that for previously published schemes, and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. The proposed technique can be extended to generate test patterns that achieve high n-detection fault coverage. This technique compresses a regular 1-detection test cube set instead of an n-detection test cube set, which is typically n times larger. Hence, the volume of compressed test data for n-detection test is comparable to that for 1-detection test. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the test sequence length, which is comparable to that of highly compacted deterministic patterns. Experimental results on n -detection test show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits.

Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits

In enhanced-scan circuits, a two-pattern test < t i , t j > for a transition fault can be obtained by using a test t j that detects a stuck-at fault, and preceding it by a test t i that activates another stuck-at fault. Thus, test generation for transition faults can be done by combining pairs of stuck-at tests. This provides an alternative to deterministic test generation, as well as reduces the test storage requirements for transition fault tests. We study the possibility of generating scan-based tests for transition faults in standard-scan circuits in a similar way, by combining pairs of stuck-at tests. Since it is not always possible to obtain a standard-scan test that is equivalent to a two-pattern test < t i , t j > based on stuck-at tests t i and t j , it is not always possible to guarantee that the combination of t i and t j will detect a transition fault. To compensate for this, it is necessary to try combinations of different stuck-at test pairs, resulting in an increased simulation effort to compute effective standard-scan tests. Our focus in this work is on reducing this simulation effort by reducing the number of stuck-at test pairs that need to be considered.

Threshold Testing: Improving Yield for Nanoscale VLSI

Yields for digital very-large-scale-integration chips have been declining in the recent years, and the decline is accelerating as the technology moves deep into nanoscale. Recently, we have proposed the notion of error tolerance to improve yields for a wide range of high-performance digital applications, including audio, speech, video, graphics, visualization, games, and wireless communication. Error tolerance systematically codifies the fact that chips used in such applications can be acceptable despite having defects that produce erroneous outputs, provided that the errors are guaranteed to be of certain types and have severities within thresholds specified by the application. In this paper, we propose a new testing approach called threshold testing to practically exploit the notion of error tolerance for applications where errors with absolute numerical magnitudes lower than an application-specified threshold are acceptable. We propose a new automatic test pattern generator (ATPG) for threshold testing for single stuck-at faults. This test generator embodies several completely new techniques, including new approaches for directing the search for a test vector, new types of objectives, new types of necessary conditions, and new approaches to identify and exploit these conditions. We demonstrate that threshold testing can enhance yield and that it is practical in terms of test generation effort and test application costs. We also propose threshold fault simulators and ATPG for bridging and transition delay faults. We use these tools to show that the stuck-at-fault model is indeed a suitable model for threshold testing. This opens the way for developing low-cost tools for threshold testing that will provide high threshold coverage for realistic faults and defects and hence help provide higher yields in future nanoscale processes at low costs.

Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures

In this work, we consider detection of errors in polynomial, dual, and normal bases arithmetic operations. Error detection is performed by recomputing with the shifted operand method, while the operation unit is in use. This scheme is efficient for pipelined architectures, particularly systolic arrays. Additionally, one semisystolic multiplier for each of the polynomial, dual, type I, and type II optimal normal bases is presented. The results show that for having better or similar space and time overheads compared to a number of related previous work, the multipliers have generally a higher error-detection capability, e.g., the error-detection capability of the RESO-based scheme for single and multiple stuck-at faults in a polynomial basis multiplier is 100 percent. Finally, we also comment on how RESO can be used for concurrent error correction to deal with transient faults.

LPTest: a Flexible Low-Power Test Pattern Generator

This paper presents a low power test pattern generator, LPTest, that minimizes the peak power consumption during the shift and capture cycles for scan-based stuck-at and transition fault testing. LPTest incorporates both power-aware ATPG and low-power X-filling techniques to achieve higher power reduction. Its enabling technique is a power estimation method which assesses the lower-bounds of the shift-in, shift-out, and capture powers of a partially specified test pattern. The lower-bound estimation method is utilized in LPTest's ATPG engine, dynamic compaction, and X-filling. LPTest has been validated using ISCAS89 benchmark circuits. When considering all cycles, LPTest achieves better than 22% peak WSA (weighted switching activity) reduction for stuck-at and transition faults compared to a commercial ATPG with high merge ratio and random-fill options. Meanwhile, the average power reduction is better than 43%. When only capture power is of concern, LPTest attains more than 46% WSA reduction for stuck-at and transitions.