Stuck-at Faults Research Articles

Bridging fault detection in cluster based FPGA by using Muller C element

In this work, we propose a testing technique for detecting single stuck-at and bridging faults in the interconnects of the cluster based FPGA. The presence of the feedback-bridging fault, race and glitch poses major challenges to the detection of the fault. The feedback bridging fault has a high ingredient of delay dependent properties due to the variation of the feedback path delay. So we have exploited the concept of asynchronous logic in order to detect the fault. We configure the block under test (BUT) with a pseudo delay independent asynchronous element known as Muller C element. The novelty of this scheme lies in the fact that, it can detect the stuck-at and bridging fault including the feedback bridging fault by a single test configuration. The Xilinx Jbits 3.0 API (Application Program Interface) is used to implement the BISTER (Built-in-self-tester) structure in the FPGA. In comparison to the traditional FPGA development tool (ISE), ‘Jbits’ gives more controllability for which the partial run time reconfiguration of the FPGA is easily achieved.

Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction

Eliminating the excessive test power for integrated circuits is a strict challenge within the nanometer era. This method combines test pattern generation with the scan chain disabling technique to achieve low capture power testing under the single stuck-at fault model. Testability analysis is exploited to assist in the test pattern generation process to generate the observation-oriented test patterns. In order to direct fault effects to the frequently-used circuit outputs, unbalanced observability costs are purposely assigned to circuit outputs to introduce unequal propagation probability. Observation-aware scan chain clustering is then performed through a weighted compatibility analysis to densely cluster the frequently-used scan cells into scan chains. Consequently, more scan chains can be disabled in the capture cycle and significant power reduction can be achieved without affecting the fault coverage. To simultaneously consider the reduction in large test data volume and capture power, the power-aware test vector compaction algorithm is also performed. Experimental results for the large ISCAS'89 benchmark circuits show that significant improvements can be simultaneously achieved including 71.7 % of capture power reduction, 43.7 % of total power reduction, 24.3 % of peak power reduction and 98.0 % of test data compaction ratios averagely. Results for three large ITC'99 benchmark circuits also demonstrate the effectiveness of the proposed method for the practical-scale circuits.

An On-Chip Clock Controller for Testing Fault in System on Chip

In this paper, an on-chip clock (OCC) controller with bypass function based on an internal phase locked loop (PLL) is designed to test the faults in system on chip (SOC), such as the transition-delay faults and the stuck-at faults. A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by the automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified. The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timing-related defects. Finally, the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

In this work, Field-Programmable Gate Array (FPGA) reconfigurability is exploited to realize autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist-Driven Evolutionary Refurbishment technique utilizes design-time information from the circuit netlist to constrain the search space of the algorithm by up to 98.1 percent in terms of the chromosome length representing reconfigurable logic elements. This facilitates refurbishment of relatively large-sized FPGA circuits as compared to previous works. Hence, the scalability issue associated with Evolvable Hardware-Based refurbishment is addressed and improved. Experiments are conducted with multiple circuits from the MCNC benchmark suite to validate the approach and assess its benefits and limitations. Successful refurbishment of the apex4 circuit having a total of 1,252 LUTs with 10 percent spares is achieved in as few as 633 generations on average when subjected to simulated randomly injected single stuck-at faults. Moreover, the use of design-time information about the circuit undergoing refurbishment is validated as means to increase the tractability of dynamic evolvable hardware techniques.

Design of Testable Reversible Sequential Circuits

In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1's, and all 0's. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The reversible design of the DET flip-flop is proposed for the first time in the literature. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum-dot cellular automata (QCA) layout of the Fredkin gate. We are also presenting a new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) that is not reversible in nature but has similar properties as the Fredkin gate of working as 2:1 multiplexer. The proposed MX-cqca gate surpasses the Fredkin gate in terms of complexity (the number of majority voters), speed, and area.

Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems

The growing density of integration and the increasing percentage of system-on-chip area occupied by embedded memories has led to an increase in the expected number of memory faults. The soft memory repair strategy proposed in this paper employs existing forward error correction at the system level and mitigates the impact of memory faults through permutation of high-sensitivity regions. The effectiveness of the proposed repair technique is evaluated on a multi-megabit de-interleaver static random access memory of an ISDB-T digital baseband orthogonal frequency-division multiplexing receiver in 65-nm CMOS. The proposed technique introduces a single multiplexer delay overhead and a configurable area overhead of ⌈M/i⌉ bits, where M is the number of memory rows and i is an integer from 1 to M, inclusive. The repair strategy achieves a measured 0.15 dB gain improvement at 2×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> quasi-error-free bit error rate in the presence of stuck-at memory faults for an additive white Gaussian noise channel.

On multi‐cycle test cubes

This article studies the generation of test sets that consist of multi-cycle test cubes. Such test cubes have partially-specified scan-in states, and several functional clock cycles between scan operations. Test cubes are important for test data compression. In addition, multi-cycle tests can detect delay defects that are not detected by single-cycle tests. The use of multi-cycle test cubes is shown to reduce the number of test cubes required for detecting single stuck-at faults compared with the case where single-cycle test cubes are used. This article also shows that a multi-cycle test cube for a single stuck-at fault can have fewer specified scan-in values than a single-cycle test cube for the same fault. As a result, multi-cycle test cubes can be more effective for test data compression. This article also discusses the conditions under which multi-cycle test cubes can be merged in order to further reduce the number of test cubes in a test set.

A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs

Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and configuration strategy however implies two opposite requirements. One one hand, a fast and scalable built-in self-testing and self-diagnosis procedure has to be carried out concurrently at NoC switches. On the other hand, programming the NoC routing mechanism to go around faulty links and switches can be optimally performed by a centralized controller with global network visibility. To the best of our knowledge, this article proposes for the first time a global network testing and configuration strategy that meets the opposite requirements by means of a fault-tolerant dual network architecture and a fast configuration algorithm for the most common failure patterns. Experimental results report an area overhead as low as 12.5% with respect to the baseline switch architecture while achieving a high degree of fault tolerance. In fact, even when multiple stuck-at faults are considered, the capability of fault masking by the dual network is always over 80%, and the support for multiple link failures is more than 90% in presence of two unusable links in the main network with minimum set-up times.

Networked-based generalised H∞ fault detection filtering for sensor faults

This paper is concerned with designing fault detection filters for networked control systems subject to limited communication capacity and a class of sensor stuck faults. By taking into account the communication limitations (e.g. measurement quantisation, signal transmission delays and data packet dropouts) and all possible sensor stuck faults, a unified mathematical model is first presented. Based on this framework, a full-order fault detection filter is designed such that the residual system is asymptotically stable with the prescribed attenuation level in the generalised H∞ sense. In order to further improve the detection performance, an optimisation algorithm is proposed to minimise the threshold. Finally, a spring-mass-damper system is utilised to show the effectiveness of the proposed method.

Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects

This study presents a new method for application testing of field programmable gate array (FPGA) interconnects at run time. This method utilises new features related to the function for the programming of the look up tables (LUTs), the utilisation (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) input/outputs (IOs) of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so-called 1-bit sum function (1-BSF); the 1-BSF detects all possible stuck-at and bridging faults (of all cardinalities) by utilising the all zeros' vector and a walking-1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4 and Virtex5), the proposed method (with a polynomial time complexity) results in a single test configuration with 100% coverage. These results also show that the proposed method requires a larger number of test vectors and an availability of unused IOs.

Antidisturbance Fault Tolerant Control of Attitude Control Systems for Microsatellite with Unknown Input Delay

The antidisturbance fault tolerant control problem of attitude control systems for microsatellite is investigated in the presence of unknown input delay, stuck faults from the reaction wheel and the multiple disturbances. The multiple disturbances are supposed to include the vibration disturbance torque from the reaction wheel and modeling uncertainties. The fault diagnosis observer and disturbance observer are constructed to estimate stuck faults and vibration disturbance torque from the reaction wheel, respectively. A composite fault tolerant controller is designed by combining a PID controller, the fault accommodation estimation based on the fault diagnosis observer, and the disturbance compensator based on the disturbance observer. The controller and observer gains can be easily obtained via a set of linear matrix inequalities. Simulation results are given to show that the faults can be accommodated readily, and the disturbances can be rejected and attenuated simultaneously.

A Novel Heuristic Method for Application-Dependent Testing of a SRAM-Based FPGA Interconnect

This paper presents a new method for generating configurations for application-dependent testing of a SRAM-based FPGA interconnect. This method connects an activating input to multiple nets, thus generating activating test vectors for detecting stuck-at, open, and bridging faults. This arrangement permits a reduction in the number of redundant configurations, thus also achieving a reduction in test time for application-dependent testing at full fault coverage. As the underlying solution requires an exponential complexity, a heuristic algorithm that is polynomial and greedy in nature (based on sorting) is used for net selection in the configuration generation process. It is proved that this algorithm has an execution complexity of O(L <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ) (where L is the number of LUTs in the design). The proposed method requires at most log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (M + 2) configurations (where M denotes the number of activating inputs) as Walsh coding is employed. Moreover, it is scalable with respect to LUT inputs. Extensive logic-based simulation results are provided for ISCAS89 sequential benchmark designs implemented on Xilinx Virtex4 FPGAs; these results shows that the proposed method achieves a considerable reduction in the number of test configurations compared with methods found in the technical literature (on average, a reduction of 49.5 percent).

Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set; this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.

Le syndrome de Pancoast et Tobias malin (à propos de 40 cas)

A group-testing-based fault resolution is incorporated into SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) to provide an evolvable hardware system with self-healing and self-organizing properties. The proposed approach employs adaptive group testing techniques to autonomously maintain FPGA resource viability information as an organic means of transient and permanent fault resolution. Reconfigurability of the SRAM-based FPGA is leveraged to locate faulty logic resources which are successively excluded by group testing using alternate device configurations. This simplifies the system architect’s role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance vs. availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an observer–controller model. The proposed group testing method operates on the output response produced for real-time operational inputs, which eliminates the need for dedicated test vectors. The proposed system was demonstrated using a Data Encryption Standard (DES) core on 4-input and 6-input LUT-based Xilinx FPGA models. With a single simulated stuck-at fault, the system identifies a completely validated replacement configuration within a few test stages. Results also include approaches for optimizing group size, resource redundancy, and availability. The approach demonstrates a readily-implemented yet robust organic hardware application that features a high degree of autonomous self-control.

Counter-Based Output Selection for Test Response Compaction

Output selection is a recently proposed test response compaction method, where only a subset of output response bits is selected for observation. It can achieve zero aliasing, full X-tolerance, and high diagnosability. One critical issue for output selection is how to implement the selection hardware. In this paper, we present a counter-based output selection scheme that employs only a counter and a multiplexer, hence involving very small area overhead and simple test control. The proposed scheme is ATPG-independent and thus can easily be incorporated into a typical design flow. Two efficient output selection algorithms are presented to determine the desired output responses, one using a single counter operation for simpler test control and the other using more counter operations for achieving a better test-response reduction ratio. Experimental results show that for stuck-at faults in large ISCAS'89 and ITC'99 benchmark circuits, 48%~90% reduction ratios on test responses can be achieved with only one counter and one multiplexer employed. Even better results, i.e., 76%~95% reductions, can be obtained for transition faults. It is also shown that the diagnostic resolution of this method is almost the same as that achieved by observing all output responses.

Robust H ∞ and adaptive tracking control against actuator faults with a linearised aircraft application

This article studies the problem of designing adaptive fault-tolerant H ∞ tracking controllers for a class of aircraft flight systems against general actuator faults and bounded perturbations. A robust adaptive state-feedback controller is constructed by a stabilising controller gain and an adaptive control gain function. Using mode-dependent Lyapunov functions, linear matrix inequality-based conditions are developed to find the controller gain such that disturbance attenuation performance is optimised. Adaptive control schemes are proposed to estimate the unknown controller parameters on-line for unparametrisable stuck faults and perturbation compensations. Based on Lyapunov stability theory, it is shown that the resulting closed-loop systems can guarantee asymptotic tracking with H ∞ performances in the presence of faults on actuators and perturbations. An application to a decoupled linearised dynamic aircraft system and its simulation results are given.

Derivation of test set for detecting multiple missing-gate faults in reversible circuits

Logic synthesis of reversible circuits has become an important problem because of its relevance to the emerging area of quantum computation. Special types of quantum gates such as k-CNOT may be deployed to implement a reversible circuit. Although the classical stuck-at fault model is widely used for modeling defects in conventional CMOS circuits, new approaches, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more befitting for modeling defects in quantum k-CNOT gates. This article presents an algorithm to derive a test set (TS) for detection of multiple missing-gate faults in a reversible circuit implemented with k-CNOT gates. It is shown that TS is sufficient to detect all single missing-gate faults (SMGFs) and all detectable repeated gate faults (RGFs). Experimental results on test set for some benchmark circuits are reported, which compare favorably with earlier findings.

FAULT DETECTION AND INTERVENTION IN BIOLOGICAL FEEDBACK NETWORKS

The study of diseases such as cancer requires the modeling of gene regulations and the loss of control associated with it. Prior work has shown that the genetic alterations in the system can be suitably modeled using different fault models (like stuck-at faults) in the Boolean Network paradigm. By studying the dynamics of the original and the faulty BN, it is possible to design intervention strategies which could drive the system from a diseased state to a less harmful one. In this paper, the method of detecting faults along with the intervention design demonstrated on a couple of real biological pathways (DNA damage pathways and osmotic stress response pathways).

Accurate X-Propagation for Test Applications by SAT-Based Reasoning

Unknown or X-values during test applications may originate from uncontrolled sequential cells or macros, from clock or A/D boundaries, or from tristate logic. The exact identification of X-value propagation paths in logic circuits is crucial in logic simulation and fault simulation. In the first case, it enables the proper assessment of expected responses and the effective and efficient handling of X-values during test response compaction. In the second case, it is important for a proper assessment of fault coverage of a given test set and consequently influences the efficiency of test pattern generation. The commonly employed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -valued logic simulation evaluates the propagation of X-values only pessimistically, i.e., the X-propagation paths found by <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -valued logic simulation are a superset of the actual propagation paths. This paper presents an efficient method for overcoming this pessimism and for determining accurately the set of signals that carry an X-value for an input pattern. As examples, it investigates the influence of this pessimism on the two applications, X-masking and stuck-at fault coverage assessment. The experimental results on benchmark and industrial circuits assess the pessimism of classic algorithms and show that these algorithms significantly overestimate the signals with X-values. The experiments show that overmasking of test data during test compression can be reduced by an accurate analysis. In stuck-at fault simulation, the coverage of the test set is increased by the proposed algorithm without incurring any overhead.

Non-Uniform Coverage by $n$-Detection Test Sets

The use of n-detection test sets increases the likelihood of defect detection. With a uniform value of for all the target faults, the expectation is that defects across the circuit will be covered uniformly. This paper demonstrates that this may not be the case by considering the four-way bridging faults detected by n-detection test sets for single stuck-at faults in benchmark circuits. Partitioning the bridging faults into subsets according to their dominated line, the results show that certain subsets have significantly lower bridging fault coverage than others. Thus, certain defect sites are significantly less covered than others. This paper also shows that it is possible to predict which subsets will have low bridging fault coverage based on the numbers of detections of single stuck-at faults under a conventional one-detection test set. This observation leads to a simplified n-detection test generation strategy. It also points to the possibility of using higher numbers of detections for certain single stuck-at faults, or targeting other fault models only at the sites that are expected to be less covered.