Stress Memorization Technique Research Articles

Process Simulation and Experimental Study of Stress Memorization in Strained Silicon nMOSFETs

Results from process simulations of the stress memorization technique (SMT) for nanoscale n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) are presented. Spatial distribution of stress components within the device were computed for different germanium dose in the pre-amorphization implant (PAI) step, different peak anneal temperatures in spike annealing and different tensile stress of the capping layer. During the spike anneal, stress is enhanced in the dielectric spacer due to viscoelastic relaxation of the capping layer. The stress induced in the channel by the spacer and the polysilicon gate after capping layer etch is non-uniform with maxima near the gate edges. Electrical measurements of fabricated SMT nMOSFETs are consistent with the simulation results.

Impact of stress-memorization technique induced-tensile strain on low frequency noise in n-channel metal-oxide-semiconductor transistors

The use of low-frequency (1/f) noise to evaluate stress-memorization technique (SMT) induced-stress in n-channel metal-oxide-semiconductor field-effect transistors is investigated. Through observing Hooge’s parameter αH, we found that the unified model can properly interpret the 1/f noise mechanism in our device. On the other hand, lower normalized input-referred noise (LSVG) level in number-fluctuation-dominated regime (region I) and smaller curvature of LSVG versus VGS-VTH in mobility-fluctuation-dominated regime (region II) are attributed to the reduced tunneling attenuation length and Coulomb scattering coefficient, respectively. It represents an intrinsic benefit of 1/f noise behavior stemming from SMT-induced more strain in short channel device.

Evaluation of Interface Property and DC Characteristics Enhancement in Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Using Stress Memorization Technique

In this letter, the advanced 40 nm technology n-channel metal–oxide–semiconductor field-effect transistor devices using the stress memorization technique (SMT) are presented. We demonstrate that SMT process would not affect the electrical characteristics of devices and can introduce higher tensile stress on channels, which enhances drive current. Through charge pumping measurement, it can be verified that SMT does not affect Si/SiO2 interface quality. Moreover, SMT-induced higher tensile stress decreases not only scattering coefficient but also tunneling attenuation length, resulting in smaller input-referred noise, which represents an intrinsic advantage of low-frequency noise performance.

Characterization of Highly Strained nFET Device Performance and Channel Mobility with SMT

This paper compares and analyzes the strained negative channel field effect transistor (nFET) device performance and the channel mobility behavior obtained by the stress memorization technique (SMT) using two different types of nitride films. These nitride film properties and wafer bowing during SMT fabrication are investigated. The electrical properties of SMT strained nFET devices including current–voltage characteristics, transconductance, carrier mobility, and interface state are also analyzed. Although SMT nitride strain can enhance electron mobility, it is critical to control the nitride properties and its hydrogen content to minimize electron mobility degradation due to interface-state generation. Thus, a simple view of the essential physics of mobility enhancement in SMT strained nFETs has been provided. Results in this work also provide guidance to further nFET performance enhancement in the ever-more challenging device targets of future technology generations.

Dependence of DC Parameters on Layout and Low-Frequency Noise Behavior in Strained-Si nMOSFETs Fabricated by Stress-Memorization Technique

The impact of stress-memorization technique (SMT)-induced tensile strain on the layout dependence of nMOSFET characteristics is investigated. It is found that the incorporation of the SMT process provides up to 12% improvement in transconductance and 9% enhancement in on-state current for nMOSFETs with a source/drain length (LS/D) of 1.76 ?m and W = 0.5 ?m. The characteristics of the SMT device become more sensitive to the layout geometry as LS/D and W are down to 0.5 and 0.25 ?m, respectively. Moreover, low-frequency measurements reveal that the interface quality of the SMT device is the same as that of the control devices. Furthermore, it is found that the mechanism of 1/f noise in the SMT device can be properly interpreted by the unified model.

Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its Mechanism

In this letter, we certify that the compressive SiN capping layer has more potential than the tensile layer for fabrication using the stress memorization technique to enhance NMOS mobility. The mechanism that we have proposed implies that the conventional choice of the capping layer should be modulated from the point of view of stress shift rather than using the highest tensile film.

Strained Silicon Technology: Mobility Enhancement and Improved Short Channel Effect Performance by Stress Memorization Technique on nFET Devices

This paper presents a fundamental study of a stress memorization technique (SMT), which utilizes a capping nitride dielectric film to enhance negative channel field-effect transistor (nFET) device performance. SMT strain engineering is highly compatible with current standard complementary metal oxide semiconductor processes without introducing substantial additional complexity. In this work, we report that SMT-strained nFET exhibits a higher transconductance , which indicates strain-induced electron mobility enhancement. The nFET short channel effect is also improved by the SMT process. Improved roll-off characteristics manifest itself and are shown to result from retarded junction diffusion as indicated by secondary-ion mass microscopy analysis. Finally, this work demonstrates that when combined with a strained contact etch stop layer (CESL) technique, SMT provides additional strain beyond that provided by the CESL, which results in further improved nFET performance.

Effect of Viscoelastic Relaxation on Stress Memorization in Strained Silicon n MOSFETs

Results from process simulations of the stress memorization technique (SMT) for nanoscale n-channel metal-oxide-semiconductor field effect transistors (n MOSFETs) are presented. The spatial distribution of stress components within the device was computed for (i) different germanium doses in the preamorphization implant step, (ii) different peak anneal temperatures in spike annealing, and (iii) different tensile stresses of the capping layer. The effect of the dielectric spacer is considered. During the spike anneal, stress is enhanced in the dielectric spacer due to the viscoelastic relaxation of the capping layer. The stress induced in the channel by the spacer and polysilicon after capping layer etch is nonuniform with maxima near the edges of the gate. Supplementary micro-Raman measurements of SMT test structures and electrical measurements of fabricated SMT devices are consistent with the simulation results.

Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.

Hole Mobility Enhancement Caused by Gate-Induced Vertical Strain in Gate-First Full-Metal High-k P-Channel Field Effect Transistors Using Ion-Beam W

In this paper, we describe a new technique of enhancing hole mobility in full-metal high-k p-channel field effect transistors (pFETs) constructed by a conventional gate-first process. A tungsten layer used as a low-resistivity gate creates a global tensile strain when it is deposited by physical vapor deposition (PVD). After the gate patterning, however, the stress in the tungsten gate modulates the local strain in the channel. If it is deposited by ion-beam PVD, the tungsten layer has a small amount of compressive stress, and does not relax the wafer-level global strain created in the W-deposition step, and eventually creates a local tensile strain after gate patterning in the horizontal (source-to-drain) and vertical (gate-to-substrate) directions. In contrast, if it is deposited by conventional PVD, the large amount of compressive stress in the tungsten gate creates a small amount of local compressive strain in the horizontal and vertical directions after gate patterning. Since the vertical tensile strain created by the ion-beam-deposited tungsten gate increases the drain current of pFETs, it can be used as a cost-effective stress memorization technique to enhance device performance.

Optimization of Stress Memorization Technique for 45 nm Complementary Metal–Oxide–Semiconductor Technology

The effect of stress memorization technique (SMT) on performance of transistors and power reduction is intensively studied. A 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously by choosing the appropriate stressor film with a large stress change by spike rapid thermal annealing (RTA). Stress distribution in the channel region for SMT is confirmed to be uniform; hence, the layout dependence is minimized and the performance is maximized in aggressively scaled complementary metal–oxide–semiconductor (CMOS) with dense gate pitch rule (190 nm) in 45 nm technology node.

Enhancement of Stress-Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering

An enhanced stress memorization-technique that utilizes a strain proximity free technique (SPFT) and a stacked-gate structure has been demonstrated by multiple strain-gate engineering. The electron mobility of n-channel metal-oxide semiconductor field effect transistors (nMOSFETs) with SPFT exhibit a 16% increase compared to that of counterpart techniques. SPFT avoids the limitation of stressor volume for performance improvement in high-density complementary metal oxide semiconductor circuits. We also found that optimization of stacked, random poly-Si-grain gate structure in combination with SPFT can improve mobility further to 22% more than a single poly-Si gate structure without SPFT.

Modeling Evolution of Temperature, Stress, Defects, and Dopant Diffusion in Silicon During Spike and Millisecond Annealing

ABSTRACTThe bulk CMOS devices continue as the dominant player for at least another couple of technology nodes. This drives the increasingly contradicting requirements for the channel, source/drain extension, and heavily doped source/drain doping profiles. To analyze and optimize the transistors, it is becoming necessary to combine a number of effects that have been treated as decoupled so far. The temperature gradients, combined with stress engineering techniques such as embedded SiGe and Si:C source/drain and stress memorization technique, create non-uniform stress distributions determined by the layout patterns. The interaction of implant-induced damage with dopants, stress, and defect traps shapes up the dopant activation, retention of useful stress, and junction leakage. This work reviews recent trends in modeling these effects using continuum and kinetic Monte Carlo methods.

Integration Challenges for Advanced Process-Strained CMOS on Biaxial-Strained-SOI (SSOI) Substrates

This work reviews the integration of process-induced stressors into transistors fabricated on biaxially-strained-SOI substrates. Tensile and compressive overlayers, embedded-SiGe, and multiple stress memorization techniques have been evaluated on strained-SOI substrates. All process-induced strain techniques are compatible with strained-SOI, except for a stress memorization technique which requires amorphization of the source/drain regions. The compatible techniques increase NMOS drive current and PMOS drive current comparably on strained-SOI and standard unstrained-SOI. This results in no loss of short channel PMOS performance but only a moderate gain in short channel NMOS performance, when SSOI is compared to standard unstrained-SOI.