Modeling Evolution of Temperature, Stress, Defects, and Dopant Diffusion in Silicon During Spike and Millisecond Annealing

Abstract

ABSTRACTThe bulk CMOS devices continue as the dominant player for at least another couple of technology nodes. This drives the increasingly contradicting requirements for the channel, source/drain extension, and heavily doped source/drain doping profiles. To analyze and optimize the transistors, it is becoming necessary to combine a number of effects that have been treated as decoupled so far. The temperature gradients, combined with stress engineering techniques such as embedded SiGe and Si:C source/drain and stress memorization technique, create non-uniform stress distributions determined by the layout patterns. The interaction of implant-induced damage with dopants, stress, and defect traps shapes up the dopant activation, retention of useful stress, and junction leakage. This work reviews recent trends in modeling these effects using continuum and kinetic Monte Carlo methods.