Stress Memorization Technique Research Articles

Significant Lifetime Improvement of Negative Bias Thermal Instability by Plasma Enhanced Atomic Layer Deposition SiN in Stress Memorization Technique

Significant Lifetime Improvement of Negative Bias Thermal Instability by Plasma Enhanced Atomic Layer Deposition SiN in Stress Memorization Technique

Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device

For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and length of diffusion effect. Based on the oxygen diffusion mechanism analysis of layout proximity effects in high-k/Metal gate NMOS device, an optimized process is proposed to suppress the layout dependency. The experiment result indicates that modified low temperature stress memorization technique process can suppress layout dependency efficiently without performance degradation of the devices.

Ultra-Wideband Low-Loss Switch Design in High-Resistivity Trap-Rich SOI With Enhanced Channel Mobility

In this paper, the stress memorization technique (SMT) effects upon ultra-wideband RF switch performance are investigated for the first time. Low insertion loss (IL), high isolation, ultra-wideband (dc to 50 GHz) single-pole double-throw (SPDT), and single-pole four-throw (SP4T) switches designed with commercial 0.13- $\mu \text{m}$ high-resistivity (HR) trap-rich SOI technology with/without SMT are presented and investigated. 2.5 V nMOS transistor ( $L_{g} = 0.2~\mu \text{m}$ ) with low $R_{\mathrm{\scriptscriptstyle ON}} {^\ast} C_{\mathrm{\scriptscriptstyle OFF}}$ from GF 130RFSOI PDK is used. It is found that channel mobility of switch transistor is improved by SMT and thus switch performance can be further improved. Moreover, the impact of transistor channel length, which has dominant effects on both IL and isolation of the switches, under different gate bias on switch performance are also studied and verified experimentally. Low measured IL of less than 2.1 dB and good isolation of better than 27 dB from dc to 50 GHz are obtained for the SPDT switch. For SP4T switch, the measured IL of less than 2.6 dB and isolation of better than 27 dB are achieved from dc to 35 GHz. The active chip areas of designed SPDT and SP4T switches are compact with size of only $0.214 \times 0.19~\text {mm}^{2}$ and $0.36 \times 0.19~ \text {mm}^{2}$ , respectively.

High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique

In this paper, strained channel-sidewall damascened tri-gate polycrystalline silicon thin-film transistors (SC-SWDTG TFTs) have been successfully fabricated and then demonstrated by an innovative process flow. This process flow without the use of advanced lithography processes combines the sidewall damascened technique (SWDT) and two strain techniques, namely, the strain proximity free technique (SPFT), and the stress memorization technique (SMT), in the poly-Si channels. It has some advantages: (1) the channel shapes and dimensions can be effectively controlled by the wet etching processes and the deposition thickness of the tetraethoxysilane (TEOS) oxide; (2) the source/drain (S/D) resistance can be significantly decreased by the formation of the raised S/D structures; (3) the SPFT, SMT, and the rapid thermal annealing (RTA) treatment can enhance the performance of the SC-SWDTG TFTs without the limitation of the highly scaling stress liner thickness in deep-submicron TFTs. Thus, the SC-SWDTG TFTs exhibit a steep subthreshold swing (S.S.) ∼ 110 mV/dec., an extremely small drain induced barrier lowing (DIBL) ∼12.2 mV V−1, and a high on/off ratio ∼107 (VD = 1 V) without plasma treatments for future three-dimensional integrated circuits (3D ICs) applications.

The dependency of different stress-level SiN capping films and the optimization of D-SMT process for the device performance booster in Ge n-FinFETs

The capping stressed SiN film is one of the most important process steps for the dislocation stress memorization technique (D-SMT), which has been used widely in the current industry, for the electron mobility booster in the n-type transistor beyond the 32/28 nm technology node. In this work, we found that the different stress-level SiN capping films influence the crystal re-growth velocities along different directions including [100] and [110] directions in Ge a lot. It can be further used to optimize the dislocation angle in the transistor during the D-SMT process and then results in the largest channel stress distribution to boost the device performance in the Ge n-FinFETs. Based on the theoretical calculation and experimental demonstration, it shows that the Ge three dimensional (3D) n-FinFETs device performance is improved ∼55% with the usage of +3 GPa tensile stressed SiN capping film. The channel stress and dislocation angle is ∼2.5 GPa and 30°, measured by the atomic force microscope-Raman technique and transmission electron microscopy, respectively.

The Demonstration of Dislocation-Stress Memorization Technique Stressor on Si n-FinFETs

The dislocation stress memorization technique (D-SMT) stressor is demonstrated to boost the device performance on the Si three-dimensional (3-D) FinFET device. The larger channel stress and mobility enhancement ratio are observed in the narrower gate width device, due to the effect of triple crystal re-growth directions on the 3-D FinFET device. In this paper, ∼33% mobility enhancement and ∼23% Id,sat improvement on the Si FinFET device with W/L of 100/60 nm are achieved successfully with the implement of D-SMT stressor.

Formation of multiple dislocations in Si solid-phase epitaxy regrowth process using stress memorization technique

This work investigates the formation mechanism of stress memorization technique (SMT)-induced edge dislocations and stacking faults during solid-phase epitaxy regrowth (SPER) using molecular dynamics (MD) simulation. During the SPER process of a patterned amorphous Si under a high-tensile capping film, growth fronts along the (110) and (001) planes collapse to form 5- and 7-rings which trigger the Frankel partial dislocation in the {111} plane. In addition, the line defects of stacking faults along {111} plane are generated with two symmetric boundaries of atomic structures which are confirmed as micro-twin defects. The MD simulation results are validated using high-resolution transmission electron microscopy and inverse fast Fourier transform images. The strain distribution obtained from the atomic structure reveals that the stress field is mainly caused by Frankel partial dislocations and the minor stress effect from the micro-twin defects.

Stacking Faults and Stress Memorization Technique Study for n-Type MOSFET Performance Improvement in All Last High-k Metal Gate Process Development

In this paper, the stacking faults, stress memorization technique (SMT) and their impacts on n-type MOSFET device performance were studied. SMT combines source/drain deep PAI improves short channel device electron mobility 25%, Ion/Ioff curve 8% and long channel device 10% and 4%, respectively. A mechanism why SMT improves device performance in all last HKMG (High-k Metal Gate) process was proposed. During SMT anneal, poly expands much more than the hard nitride cap, the thermal stress gain from poly transformation from an elastic state to a plastic state was transferred into the channel, the stress was then memorized by the source/drain stacking faults, that were formed during the SMT anneal at deep pre-amorphous source/drain area. After poly removal, the tensile stress still exists, as it was retained by the stacking faults. The stress intensity along channel, Sxx, is the key parameter to index the stress effect on device performance improvement; it is related to poly volume and gate length. And based on this, the reasons that long channel and short channel devices performance gain are much smaller than that of the middle channel devices were also discussed.

Characterization of Oxide Traps in 28 nm n-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Different Uniaxial Tensile Stresses Utilizing Random Telegraph Noise

In this study, the effect of uniaxial tensile on the SiO2/Si interface of the 28 nm n-type metal–oxide–semiconductor field-effect transistors (nMOSFETs) has been investigated. nMOSFETs were fabricated with different thicknesses of the stress-memorization technique (SMT) films to further increase channel stress because the SMT films can provide a higher uniaxial tensile to the channel. Trap behaviors such as activation energy and depth were characterized on the basis of drain current random telegraph noise (RTN). By RTN analyses, we found that the trap energy level is closer to the channel conduction band as the tensile strain in the channel increases higher, resulting in the trap being located close to the SiO2/Si interface.

Enhanced Degradation by Negative Bias Temperature Stress in Si Nanowire Transistor

Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.

Performance Improvement by Stress Memorization Technique in Trigate Silicon Nanowire MOSFETs

We achieved significant on-current improvement in trigate silicon nanowire transistors by applying stress memorization technique (SMT). We found that the performance improvement by SMT in 〈110〉-oriented nanowire nFETs is caused by both the mobility improvement due to vertical compressive strain and the parasitic resistance reduction due to positive fixed charges at the gate edge induced by SMT process. Mobility increase ratio by SMT increases with reducing the nanowire width due to the enhanced strain. Although both the mobility and the parasitic resistance are degraded by SMT in pFETs, much larger performance improvement in nFETs leads to the improvement of total CMOS performance by SMT.

Extension of Moore's Law via Strained Technologies- The Strategies and Challenges

In this paper, we will first give an overview on the strain-silicon technology, such as eSiGe, eSi:C, stress memorization technique (SMT), dual stress liners (DSL), and high-k/metal gate replacement gate (RMG) process, after the 90nm generation. Then, the reliability and the design guideline for a trade-off between performance and reliability will be addressed. A technology roadmap in terms of the ballistic transport theory will be outlined. Then, the variability of the strained CMOS devices with focus on the discrete dopant profiling will be demonstrated. Finally, the strategies of strained-silicon device on advanced 3D device structure and IC will be introduced.

Origin of Stress Memorization Mechanism in Strained-Si nMOSFETs Using a Low-Cost Stress-Memorization Technique

Implementation of strained-Si MOSFETs with optimum low-cost stress-memorization technique for a 40-nm technology CMOS process was demonstrated. Devices fabricated on (1 0 0) substrate with 〈1 0 0〉channel orientation provide additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The stress-memorization technique (SMT) mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain L <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> and polyspacing) on the device performance. In the SMT devices with L <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> down to 0.11 μm and polyspace reduced to 120 nm, no obvious current improvement and more performance degradation are observed compared with control device (only strained contact etch-stop layer), indicating that the benefit of the SMT is substantially eliminated and showing that the SMT-induced stress is mainly originated from the source/drain region in our case.

Temperature Dependence of Electrical Characteristics of Strained nMOSFETs Using Stress Memorization Technique

The temperature dependence of the electrical characteristics of strained nMOSFETs combining stress memorization technique (SMT) process and contact etch-stop layer has been investigated. The observed higher mobility and lower gate tunneling current of SMT devices indicate higher tensile stress in the channel and prove the true transmission of SMT-process-induced stress from the deposited SiN layer. Moreover, as temperature is increased, SMT devices show less deteriorated mobility and increased gate tunneling current, which are due to decreased phonon scattering and increased tunneling barrier height, respectively.

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal–oxide–semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new high-mobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III–V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies.

Mechanism of Stress Memorization Technique (SMT) and Method to Maximize Its Effect

A simple and unified fundamental theory on the mechanism of stress memorization technique (SMT) is presented for the first time. This theory is based on the difference in thermal properties of the materials involved in SMT process, i.e., silicon (channel), polysilicon (gate), amorphous silicon (source/drain), SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (gate oxide), as well as Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> (SMT nitride stressor layer), which lead to deformations during thermal anneal and SMT. This theory accounts for all the results published to date in SMT and provides important physical insights. As a demonstration of predictive capability of this theory, a 45-nm process was modified using a novel anneal sequence which raises the stress in the channel. The experimental data after the change yield additional 5% performance boost for NFET compared to a baseline SMT process.

Characterization of Enhanced Stress Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering

To extend a carrier mobility improvement by strain engineering in high-density and small-gate-space complementary metal-oxide-semiconductor (CMOS) circuits, we have proposed a new stress memorization technique (SMT) that uses a strain proximity free technique (SPFT) to demonstrate the mobility improvement through multiple strain-gate engineering. The electron mobility of n-channel metal-oxide-semiconductor (MOS) field-effect transistors with the SPFT exhibits a 14% increase over counterpart techniques. Compared with the conventional SMT, the SPFT avoids the limitation of the stressor volume for the performance improvement in high-density CMOS circuits. We also found that the preamorphous layer (PAL) gate structure in combination with the SPFT can improve the mobility further to 31% greater than standard devices. Moreover, an additional 30% mobility enhancement can be achieved by using a dynamic threshold-voltage MOS and combining the PAL gate structure with the SPFT, respectively. The gate-oxide reliability and the channel-hot-carrier reliability are also analyzed. Our results show a mobility improvement by the SPFT, a slightly increased gate leakage current, and degraded channel-hot-carrier reliability.

Investigation of Stress Memorization Process on Low-Frequency Noise Performance for Strained Si n-Type Metal–Oxide–Semiconductor Field-Effect Transistors

The use of low-frequency (1/f) noise to evaluate low-cost stress-memorization technique (SMT) induced-stress in n-type metal–oxide–semiconductor field-effect transistors has been investigated. As compared to device without SMT process, the comparable 1/f noise level obtained for strained Si devices with the low-cost SMT process indicates that adding the low-cost SMT process will not affect the Si/SiO2 interface quality. Moreover, through observing experiment result and Hooge's parameter αH, the mechanism of 1/f noise in the both devices can be properly interpreted by the carrier number fluctuations correlated mobility fluctuations (unified model).

Impact of Strain Layer on Gate Leakage and Interface-State for nMOSFETs Fabricated by Stress-Memorization Technique

This paper investigates the impact of stress memorization on the interface-state for n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETS). We found that both the initial component of the deposited capping layer and the H released during annealing affected interface-state passivation. The annealed stress is responsible for degraded gate-leakage characteristics. Based on electrical performance and gate leakage, an initial compressive layer of SiN performs better than an initial tensile layer for the stress-memorization technique process.