Mechanism of Stress Memorization Technique (SMT) and Method to Maximize Its Effect

Abstract

A simple and unified fundamental theory on the mechanism of stress memorization technique (SMT) is presented for the first time. This theory is based on the difference in thermal properties of the materials involved in SMT process, i.e., silicon (channel), polysilicon (gate), amorphous silicon (source/drain), SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (gate oxide), as well as Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> (SMT nitride stressor layer), which lead to deformations during thermal anneal and SMT. This theory accounts for all the results published to date in SMT and provides important physical insights. As a demonstration of predictive capability of this theory, a 45-nm process was modified using a novel anneal sequence which raises the stress in the channel. The experimental data after the change yield additional 5% performance boost for NFET compared to a baseline SMT process.