Abstract
For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and length of diffusion effect. Based on the oxygen diffusion mechanism analysis of layout proximity effects in high-k/Metal gate NMOS device, an optimized process is proposed to suppress the layout dependency. The experiment result indicates that modified low temperature stress memorization technique process can suppress layout dependency efficiently without performance degradation of the devices.
Highlights
The effects of process-induced stress enhancements on transistor performance are becoming increasingly important to advanced CMOS technology
For the technology nodes above the 40 nm, stress memorization technique (SMT) by dislocation is widely used for performance boost in high-k metal-gate nMOSFET [1]–[3]
Most of researches on SMT has focused on improving the mobility of nMOSFETs, while very few studies have been identified that have reported on layout proximity effects (LPEs) stemming from stress process
Summary
The effects of process-induced stress enhancements on transistor performance are becoming increasingly important to advanced CMOS technology. For the technology nodes above the 40 nm, stress memorization technique (SMT) by dislocation is widely used for performance boost in high-k metal-gate nMOSFET (including planer device and bulk FinFET) [1]–[3]. Several previously negligible physical effects are becoming increasingly important as a result of the high temperature annealing in the SMT process. Layout proximity effects (LPEs) have become a non-negligible problem having impact on the performance of device [4]–[6]. The notable LPEs induced by the SMT process in planer HKMG (high-k first/metal gate last) nMOSFETs are systematically studied, including the width effect (W) and the different shallow trench spacing (DSTS) effect.The DSTS includes DSTS-X (along the channel length direction) and DSTS-Y (along the channel width direction) [7]. A modified SMT process flow for suppressing LPE is proposed
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