Stress-induced Leakage Current Research Articles

Impact of Deuterium and Fluorine Incorporation on Weibull Distribution of Dielectric Breakdown in Gate Dielectrics

TDDB (Time-Dependent Dielectric Breakdown) is still serious in the context of efforts to realize highly reliable ULSI. In particular, the statistical distribution of TDDB is essentially important from the viewpoint of determining the lifetime of the devices. In this work, we focus on the effect of deuterium (D) and fluorine (F) incorporation into gate oxides on TDDB statistics. These elements can terminate (passivate) dangling bonds of silicon or oxygen in SiO2 and its interface. As a result, stress-induced leakage current (SILC) is suppressed by deuterium incorporation, and consequently, Weibull distribution of Tbd shifts to long lifetime maintaining Weibull slope. Furthermore, Weibull slope monotonously increases with increasing fluorine dosage. On the basis of experimental results, the suppression of probability of Si-H bond breakage and the structural relaxation of SiO2 network invoke the improvement of Weibull distribution of Tbd.

Low Voltage SILC Analysis for High-k/metal Gate Dielectrics

Conduction behavior of multi-layer structure of metal/high-k/interfacial layer gate stacks was investigated before and after constant voltage stress. It was found that stress-induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-SILC) was analyzed systematically with gate stacks of different interfacial layer thicknesses and SiO2-only devices of identical processing condition. Based on the results of defect generation sensed by the LV-SILC, it is observed that discrete levels of trap generation in the interfacial layer primarily causes low voltage SILC in metal/high-k gate stacks and initiates the gate stack breakdown.

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL (gate-induced drain leakage current) stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC (stress induced leakage current) in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.

Correlation of Charge Buildup and Stress-Induced Leakage Current in Cerium Oxide Films Grown on Ge (100) Substrates

High-kappa films are currently deposited on Ge substrates to compensate the mobility loss, as Ge offers higher mobility compared with that of silicon. This paper deals with the reliability characteristics of cerium oxide films grown by molecular beam deposition on n-type Ge (100) substrates. MOS capacitors with Pt gate electrodes were subjected to constant voltage stress conditions at accumulation. The correlation of the charge-trapping characteristics and the stress-induced leakage current (SILC) to the applied field is observed and analyzed. The results suggest that one major problem for the potential use of rare earth oxides in future MOS technology is the existence of relaxation effects. The cross-sectional value of the bulk oxide traps is on the order of 10-18 cm2 , thus indicating neutral defects. Direct comparison to reported results on high- kappa/Si and SiO2/Si structures shows that SILC properties are related to the quality of the dielectric layers; the semiconductor substrate is immaterial.

Analysis of the improvement of Al–Ta 2O 5/SiO 2–Si structures reliability by Si substrate plasma nitridation in N 2O

Reliability properties of 30-nm thick insulating films grown by thermal oxydation of Ta deposited on plasma nitrided Si for times varying from 5 to 15 s were studied for the case of constant current stresses. Stress-induced leakage currents of thus obtained Ta 2O 5/SiO xN y stacked layers with the stress were monitored by the evolution of the parameters extracted with the use of our recently developed comprehensive model for leakage currents. It is concluded that the nitridation of the substrate prior to the Ta 2O 5 formation, simultaneously with the increase of the dielectric constant of the stack and the decrease of the leakage currents in fresh samples, improves the reliability properties against constant current stress. The increased charges to breakdown and the decreased trapping in the insulating film were explained by the improved resistance of the interface with substrate to the stress due to the incorporation of a small amount of nitrogen atoms. Since the N atoms are much stronger bonded to the Si substrate, the nitrided interface becomes more resistant to the stress. The optimum observed for nitridation times of about 10 s was explained by the strengthening of the interface with N-atoms without excessive growth of the SiO xN y–Si interfacial layer and without excessive lowering of its injection barriers.

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide is investigated under the low gate voltage stress (LGVS) and peak substrate current (Isub, max) stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage (GIDL) current and stress induced leakage current (SILC). The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub, max stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.

Stress-induced leakage current and random telegraph signal

Stress-induced leakage current (SILC) and random telegraph signal (RTS) in n-type metal-oxide-semiconductor field-effect-transistor (n-MOSFETs) caused by the Fowler-Nordheim tunneling stress are studied by using the author’s newly developed test pattern. MOSFETs having large RTS increase can be induced by electrical stress in parallel with the inducing of SILC. Generation and recovery characteristics of SILC and RTS against the stress time and measurement temperature are very similar. However, the MOSFETs having large RTS are not related to ones having large anomalous SILC in this study. We consider that the traps that cause the RTS and anomalous SILC are the same, but their locations in SiO2 are different.

Impact of progressive oxide soft breakdown on metal oxide semiconductor parameters: Experiment and modeling

The impact of a soft breakdown-induced leaky weak spot occurring in the channel has been analyzed by two dimensional simulations of a metal oxide semiconductor field effect transistor within the charge sheet approximation. The model proves very efficient in reproducing the device characteristics variations after soft breakdown (SBD) and enables to properly interpret the correlation observed between device parameter shift (e.g., threshold voltage) and stress-induced gate leakage current. A partitioning study allows us to extract an expression for the channel debiasing at Vd>0 and to discriminate each impact of SBD on device characteristics.

Constant current stress of Ti-doped Ta2O5 on nitrided Si

The response of Ti-doped Ta2O5 stacked films (4–6 nm) to constant current stress (CCS) under gate injection has been investigated. Two doping methods (‘surface’ and ‘bulk’ doping of Ta2O5) as well as two Si-surface nitridation processes (rapid thermal annealing in N2O and NH3) have been used to prepare the stacks. The effect of doping approach, Si-surface nitridation and the metal electrode (Al and W) on the dielectric degradation has been discussed in terms of stress-induced leakage current (SILC), stress-induced flat band voltage shifts, charge trapping and defect generation. CCS generates charges in the bulk dielectric and in slow states, whose sign and amount depend on both the nitridation process and the doping approach. The method of doping has the strongest impact on the SILC whose behaviour is found to be substantially different from that in SiO2. The method of doping plays a crucial role in the CCS degradation and can be used as an enabling tool for control of this degradation. The gate-deposition-induced defects are another key factor which controls the stress degradation. These defects are very susceptible to electrical stress and could lead to serious reliability concerns.

Temperature Effects on Breakdown Characteristics of High-$\kappa$ Gate Dielectrics With Metal Gates

In this paper, the temperature dependence of time-dependent dielectric breakdown (BD) and stress-induced leakage current (SILC) of high-kappa and interfacial layers (ILs) are studied separately and in a gate stack with metal gates as the BD mechanisms of these layers are different at higher temperatures than at room temperature. As observed from the low voltage SILC, the IL initiates the gate stack BD process at elevated temperature, which is followed by the high-kappa layer. Activation energy extracted from Weibulll distribution of time-to-BD (T BD) data from high-kappa layer further suggests that the gate stack BD occurs when high- kappa layer ultimately breaks down.

Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

In the present work we study reliability issues of Pt/HfO2/Dy2O3/n-Ge MOS structures under various stress conditions. The electrical characteristics of the micro-capacitors are very good probably due to the presence of a rare earth oxide as interfacial layer. It is shown that the injected charge (Qinj) at high constant voltage stress (CVS) conditions induces stress-induced leakage current (SILC) that obeys a power-law. We also observe a correlation between the trapped oxide charge and SILC, which is, at low stress field, charge build-up and no SILC, while at high stress field SILC but few trapped charges. Results show that the present bilayer oxides combination can lead to Ge based MOS devices that show acceptable degradation of electrical properties of MOS structures and improved reliability characteristics.

Electrical Characteristics and Thermal Stability of $ \hbox{Hf}_{x}\hbox{Ta}_{y}\hbox{Si}_{z}\hbox{N}$ Metal Gate Electrode for Advanced MOS Devices

To continuously improve device performance with the shrinkage of device dimension, some novel devices like fully depleted silicon-on-insulator and symmetric double-gate transistor have been proposed. Various HfxTaySizN metal gate electrodes were developed in this paper to achieve work function near the midgap and excellent thermal stability. Furthermore, this paper also demonstrated a good metal gate candidate, Hf0.19Ta0.41Si0.26N0.14, possessing excellent electrical performances in hysteresis effect, interface trap density, stress-induced leakage current, and excellent thermal stability as well.

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.

Two-trap model for low voltage stress-induced leakage current in ultrathin SiON dielectrics

Stress-induced leakage current is a useful probe of the buildup of trap states created by the electrical stress of ultrathin dielectric films. The generation of both bulk and interface traps can affect the current-voltage characteristics. It has been shown that trap assisted tunneling through interface traps is the dominant transport mechanism below 3.5 nm thickness when the poststress leakage is sensed in the off state. However, there is some ambiguity in the literature regarding whether traps at one or both of the contact interfaces are involved in the tunneling process. In this work, we show that for n-channel metal-oxide-semiconductor (NMOS) devices, the off-state (VG<0 V) gate current of electrically stressed ultrathin SiON dielectrics senses a two-trap tunneling process that involves interface states at both anode and cathode interfaces. In aggregate, five peaks due to tunneling via interface traps are observed in the poststress I-V characteristics of ultrathin NMOS SiON dielectrics.

Degradation and Breakdown of W–La2O3 Stack after Annealing in N2

We report the effect of relatively high-voltage stressing (under substrate injection) on the stress-induced leakage current (SILC) and breakdown of W–La2O3 stacked structures. It is shown that the gate area of the metal–insulator–semiconductor (MIS) devices under evaluation influences their final degradation characteristics after stress. Once the samples reach breakdown, their post-breakdown current–voltage (I–V) characteristics suggest that leakage spots are highly localized and are caused by the accumulation of defects.

NMOSFET의 제조를 위한 습식산화막과 질화산화막 특성에 관한 연구

본 논문에서는 핫 케리어 효과, 항복전압 전하, 트랜지스터 Id Vg 특성곡선, 전하 트래핑, SILC와 같은 특성들을 비교하기 위하여 HP 4145 디바이스 테스터를 사용하여 습식 산화막과 질화 산화막으로된 <TEX>$0.2{\mu}m$</TEX> NMOSFET를 만들어 측정하였다. 그 결과 질화 산화막으로 만들어진 디바이스가 핫 케리어 수명(질화 산화막은 30년 이상인 반면에 습식 산화막 소자는 0.1년임), Vg의 변화, 항복전압, 전계 시뮬레이션, 전하 트래핑면에서도 습식 산화막 소자보다 우수한 결과를 얻을 수 있었다. In this paper we fabricated and measured the <TEX>$0.26{\mu}m$</TEX> NMOSFET with wet gate oxide and nitride oxide gate to compare that the charateristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve, charge trapping, and SILC(Stress Induced Leakage Current) using the HP4145 device tester. As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially hot carrier lifetime(nitride oxide gate device satisfied 30 years, but the lifetime of wet gate oxide was only 0.1 year), variation of Vg, charge to breakdown, electric field simulation and charge trapping etc.

Degradation behavior of Ta 2O 5 stacks and its dependence on the gate electrode

Response of 8 nm Ta 2O 5 stacks with Al and Au gate electrodes to voltage stress at room temperature and at 100 °C is investigated. Stress-induced leakage current (SILC) reveals significant gate dependence and distinct difference to SILC in SiO 2. The mechanisms for SILC generation and stress degradation are discussed. Unlike SiO 2, pre-existing traps and positive charge build-up are recognized as a key factor for generation of SILC in Ta 2O 5 stacks.

Deep-Trap Stress Induced Leakage Current Model for Nominal and Weak Oxides

We have developed a model of the stress-induced leakage current (SILC) based on the inelastic trap-assisted tunneling (ITAT) by introducing a trap with a deep energy level of 3.6 eV from the bottom of the conduction band. This model can explain both of two field dependencies, i.e., a field dependence of the direct tunneling (DT) for A-mode SILC and that of the Fowler–Nordheim (FN) tunneling for B-mode SILC by analytical equations of a common form. For simple analytical equations, we introduce the most favorable trap position (MFTP), which gives the largest contribution to the leakage current. The trap area density for A-mode SILC of around 1×1010 cm-2 and the area density of the leakage paths for B-mode SILC of 1×102 cm-2 were obtained by comparisons between the experimental results and the present model.

Constant voltage stress induced current in Ta2O5 stacks and its dependence on a gate electrode

Response of 8 nm Ta2O5 stacks with different gates (Al, W and Au) to voltage stress at gate injection is studied by probing under various voltage/time conditions at room temperature and at 100 °C. A stress-induced leakage current (SILC) is detected in all samples and reveals gate dependence. It is established that the pre-existing traps actually govern this response, and the impact of gate-induced defects is stronger. The Au-gated devices are the most susceptible to the stress degradation. Two processes—electron trapping at pre-existing traps and positive charge build-up—are suggested to be responsible for generation of SILC. It is concluded that despite some gate effects, the origin of CVS degradation in this particular high-k dielectric is different from that in SiO2.

Breakdown Characteristics of High-k Gate Dielectrics with Metal Gates

Considering the breakdown mechanisms of high-k and interfacial (IL) layers are different at higher temperatures than at room temperature, in this work the temperature dependence of stress induced leakage current (SILC) and time dependent dielectric breakdown (TDDB) of theses layers are studied separately. As observed from the low voltage SILC, the interfacial layer initiates the gate stack breakdown process at elevated temperature which is followed by the high-κ layer. Activation energy extracted from Weibulll distribution of time-to-breakdown (TBD) data from high-k layer further suggests that the gate stack breakdown occurs when high-k layer ultimately breaks down.