Abstract
Response of 8 nm Ta2O5 stacks with different gates (Al, W and Au) to voltage stress at gate injection is studied by probing under various voltage/time conditions at room temperature and at 100 °C. A stress-induced leakage current (SILC) is detected in all samples and reveals gate dependence. It is established that the pre-existing traps actually govern this response, and the impact of gate-induced defects is stronger. The Au-gated devices are the most susceptible to the stress degradation. Two processes—electron trapping at pre-existing traps and positive charge build-up—are suggested to be responsible for generation of SILC. It is concluded that despite some gate effects, the origin of CVS degradation in this particular high-k dielectric is different from that in SiO2.
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