Wafer Stress Research Articles

Effect of micromorphology on measurement of residual stress of ground silicon wafers using Raman spectroscopy

Effect of micromorphology on measurement of residual stress of ground silicon wafers using Raman spectroscopy

The Force-Frequency Characteristics of Quartz Wafers under a Cantilever Beam Structure.

This study investigated the force-frequency characteristics of quartz wafers inside a cantilever beam frame. Firstly, the force-frequency coefficient formula of quartz wafers with fixed ends under axial force was analyzed. Firstly, the formula for the force-frequency coefficient of quartz wafers with fixed ends under axial force was analyzed. A force-frequency coefficient formula suitable for cantilever beam structures was derived by considering the changes in surface stress and stiffness of quartz wafers with fixed ends and one end under force on the other. Subsequently, the formula's accuracy was verified by experiments, and the accuracy was more than 92%. In addition, strain simulation analysis was performed on three different shapes of quartz wafers, and experimental verification was carried out on two of them. The results revealed that trapezoidal quartz wafers and cantilever beam structures exhibited superior stress distribution to rectangular chips. Furthermore, by positioning electrodes at various locations on the surface of the quartz chip, it was observed that, as the electrodes moved closer to the fixed end, the force-frequency coefficient of the rectangular quartz chip increased, along with an increase in chip strain under the cantilever structure. In summary, this study provides a new approach for designing cantilever quartz resonator sensors in the future.

The effect of RTP pretreatment on slip-lines of argon annealed silicon wafer

In this research, Rapid Thermal Process (RTP) pretreatment technology was used to study the slip-lines of 12-inch light boron-doped silicon wafer with Oxidation Induced Stacking Fault (OISF) ring which will be used for argon annealing. X-ray Diffraction Topography (XRT) test results were shown that Rapid Thermal Processing (RTP) pretreatment below 1250 °C would lead to the deterioration of slip-lines during argon annealing, and that RTP pretreatment no less than 1250 °C would eliminate slip-lines. Bulk Micro Defects (BMD) tests show that RTP pretreatment can deteriorate or eliminate slip-lines resulted from argon annealing. When the RTP pretreatment temperature is lower than 1250 °C, the native BMD nuclei smaller than the critical size will eliminate. During argon annealing, the growth of the residual native BMD nuclei formed during ingot pulling process is the dominant process, while formation and growth of new nuclei are less, resulting in both the reduction of BMD density and broadening distribution of BMD size. Then we see the slip-lines of silicon wafer will become worse due to the increase of thermal stress in the silicon wafer. However, when the RTP pretreatment temperature is no less than 1250 °C, the native BMD nuclei will be completely eliminated and a vacancy enriched layer will be formed in the silicon wafer. During argon annealing, vacancies promote the uniform nucleation of BMD, the density of BMD increases and the size distribution becomes narrow, and the thermal stress in the silicon wafer is relatively lower, thus the slip-lines are eliminated.

Characterization of Residual Stress in SOI Wafers by Using MEMS Cantilever Beams.

Silicon-on-insulator (SOI) wafers are crucial raw materials in the manufacturing process of microelectromechanical systems (MEMS). Residual stresses generated inside the wafers during the fabrication process can seriously affect the performance, reliability, and yield of MEMS devices. In this paper, a low-cost method based on mechanical modeling is proposed to characterize the residual stresses in SOI wafers in order to calculate the residual stress values based on the deformation of the beams. Based on this method, the residual strain of the MEMS beam, and thus the residual stress in the SOI wafer, were experimentally determined. The results were also compared with the residual stress results calculated from the deflection of the rotating beam to demonstrate the validity of the results obtained by this method. This method provides valuable theoretical reference and data support for the design and optimization of devices based on SOI-MEMS technology. It provides a lower-cost solution for the residual stress measurement technique, making it available for a wide range of applications.

Modeling and experimental investigation of monocrystalline silicon wafer cut by diamond wire saw

Diamond wire sawing is one of the key technologies in solar cell manufacturing process and semiconductor chip manufacturing process. The thinned of silicon wafer has become a development trend of semiconductor industry, and the reduction of silicon wafer thickness can improve the material utilization and reduce the manufacturing cost. Therefore, the minimum thickness analytical model of diamond wire saw cutting monocrystalline silicon wafer is proposed in this paper to study the processing mechanism of minimum thickness of monocrystalline silicon wafer. Firstly, based on the Kirchhoff’s thin plate theory, the theoretical equation of the maximum internal stress of single silicon wafer and the sawing thickness of the silicon wafer is derived from the sawing force model. Combined with the Mohr’s strength theory, the analytical model of minimum sawing thickness of monocrystalline silicon wafer is established. Then, the analytical model is verified by the finite element simulation. The average error between the simulation results and the calculation results of the analytical model about the minimum sawing thickness of silicon wafer is 9%. Finally, the monocrystalline silicon sawing verification experiments are conducted under some groups of processing conditions. The experimental results show that the minimum sawing thickness of the silicon wafer decreases with the increasing axial speed of the wire saw, increases with the increase of the feed rate of the wire saw, and decreases first and then increases with workpiece speed becoming large. The average error of the experimental results and the calculation results of the analytical model of the wafer minimum sawing thickness is 7.4%, which verifies corrections of the analytical model.

Synthesis of Al2O3/SiO2 core–shell composite abrasives toward ultrasmooth and high-efficiency polishing for sapphire wafers

A novel Al2O3/SiO2 core–shell composite abrasive was successfully synthesized via a facile sol–gel strategy and utilized to promote the surface quality and polishing efficiency of sapphire wafer. The silica shell with dense and amorphous structure was successfully coated on Al2O3 core. Its synthesis mechanism was discussed deeply, and good dispersibility and uniform particle size were obtained. The acquired core–shell composite particles were employed for the planarization machining of sapphire wafer. Results show that the decrease in surface roughness of Al2O3/SiO2 core–shell composite abrasives during polishing is more than 20.2% of that of pure Al2O3 abrasives, the material removal rate is more than 5.1% of that of pure Al2O3 abrasives, and the residual stress of the sapphire wafer finished by composite abrasives is decreased by approximately 40%. These results demonstrate that the Al2O3/SiO2 core–shell composite abrasives provide a more excellent polishing performance for the sapphire wafer, resulting in smoother and scratch-free surface with a higher material removal rate compared with pure Al2O3 abrasives. On the basis of the reaction product analysis and elastic-plastic micro-contact mechanics, the reasons for the improvement of polishing performance were revealed in terms of chemical corrosion and mechanical abrasion.

Iterative method for obtaining nonuniform grinding-induced residual stress distribution of silicon wafers based on global deformation

Grinding as the main thinning process for silicon wafers is widely used in chip manufacturing. The residual stress distribution is desired to be known to optimize the grinding process. In this paper, an iterative method for obtaining the nonuniform residual stress of ground silicon wafers was proposed. The deformation of ground silicon wafers was divided into two parts in which one part was large spherical deformation and the other was a small out-of-sphere deformation. The spherical deformation which was in the nonlinear range corresponded to an average stress which was obtained using the bisection method. The small out-of-sphere deformation corresponded to the stress variation which was obtained using the regularization method with continuity constraints. An iterative successive approximation process was conducted to address the nonlinear problem which was transformed into a local linear problem. The residual stress distribution of a ground silicon wafer was obtained successfully using the proposed method. Although the overall shape of the wafer deformation was approximately spherical, the residual stress value varied a lot with the crystal orientation of the silicon wafer. The stress values in the <110> orientations were much larger than those in the <100> orientations. The method could be used to evaluate the grinding process independently of the dimension sizes of ground silicon wafers. The proposed method in this paper is non-destructive and could be used to track the residual stress changes in the grinding process and the process parameters could be optimized accordingly.

Quantifying the subsurface damage and residual stress in ground silicon wafer using laser ultrasonic technology: A Bayesian approach

Dispersion nature of surface acoustic waves (SAWs) propagating along the machined surface contains key information about the elastic properties and stress state of the subsurface damage (SSD) layer. This enables the acoustical characterization of SSD. In this paper, we develop a mechanical properties and residual stress estimation technology for the machined surfaces, especially for ground silicon wafer, based on laser-excited surface acoustic waves (LSAWs). Bayesian inversion is applied to quantify nine orthotropic elastic constants and one residual stress parameter of the SSD layer together with the corresponding uncertainty estimates from dispersion data. The forward model of SAW propagation is derived based on Biot’s theory of small deformations influenced by initial stress. The solution of the inverse problem is given in terms of the posterior probability density (PPD) of the SSD model parameters. Markov chain Monte Carlo (MCMC) method is used to generate posterior samples by repeatedly solving the forward model to compute parameter uncertainties and inter-relationships. Laser ultrasonic experiments have been performed on two typical areas of the ground silicon wafer to determine the ability of the technology to characterize SSD and residual stress and the effect of grinding direction on the damage degree of SSD. The elastic constant values estimated by the proposed method can be reasonably explained by the fracture properties of single-crystal silicon. The reliability of the results is further verified via nanoindentation and micro-Raman spectroscopy.

Study on the processing characteristics of sapphire wafer polished with different properties plates

To realize the processing demands of the sapphire wafer surface with scratch-free and nano-scale roughness by mechanical polishing, a novel flexible polishing plate was developed by using soft unsaturated resin. The surface characteristics, material removal rate, and residual stress of the sapphire wafer after the flexible polishing process have been compared with those of the sapphire wafer after the rigid polishing process. Both theoretical and simulation analysis results show that the abrasive particles in the flexible polishing exhibit an apparent yielding effect during the polishing course, which contributes to the achievement of plastic flow removal for the wafer surface. The experimental results show that the surface roughness and subsurface damage of the sapphire wafer polished by the flexible polishing process can be decreased by 18.7% and 57.3%, respectively, compared with those of the sapphire wafer polished by the rigid polishing process.

Impact of the temperature process on the morphology of 3D temporary bonded wafers: Quantification and reducing of the effect

300 mm diameter thinned-down wafers are manufactured using temporary adhesive bonding. A thermoplastic adhesive and a silicon carrier are used to fabricate 100 μm thick silicon wafers. The impact of temperature on the thickness homogeneity of temporary bonded stacks is studied. From 150 °C up to 300 °C, the total thickness of the structure increases with the temperature. Moreover, its amplitude strongly increases with the thinned wafer stress and the adhesive thickness. On the contrary, it does not depend on the different interface adherence. The thinned wafer stress results in a significant peeling force which drives the deformation of the structure. This deformation is possible because of the high elasticity of the polymer at high temperature. To reduce this deformation, an alternative carrier is proposed yielding reduction of the adhesive thickness at the bonded edge only.

Effect of the thermal stress on the defect evolution at GaAs/Si wafer bonding with a-Ge intermediate layer

In this paper, the bonding of GaAs wafer and Si wafer is achieved by introducing an amorphous Ge as the intermediate layer. Dislocations are observed on the GaAs surface when the GaAs/Si bonded wafers are annealed at 150 °C. The dislocation density is found to increase with the increase of the annealing temperature (from 150 °C to 350 °C). This feature can be explained by the increase of the thermal stress in the GaAs wafer due to the thermal mismatch between GaAs and Si wafers. With higher annealing temperature, such as 300 °C and 350 °C, some pits which originate from the partial cracking of GaAs surface are observed at the boundary of the bonded and unbonded regions. According to the stress simulation, the thermal stress at the bonding interface increases rapidly and reaches its maximum near the boundary of the bonded and unbonded regions, leading to the cracking of GaAs surface (formation of pits). In addition, large numbers of dislocations are generated near the pits. This may be attributed to the reduction of the nucleation energy of dislocations.

The Influence of Wire Speed on Phase Transitions and Residual Stress in Single Crystal Silicon Wafers Sawn by Resin Bonded Diamond Wire Saw.

Lower warp is required for the single crystal silicon wafers sawn by a fixed diamond wire saw with the thinness of a silicon wafer. The residual stress in the surface layer of the silicon wafer is the primary reason for warp, which is generated by the phase transitions, elastic-plastic deformation, and non-uniform distribution of thermal energy during wire sawing. In this paper, an experiment of multi-wire sawing single crystal silicon is carried out, and the Raman spectra technique is used to detect the phase transitions and residual stress in the surface layer of the silicon wafers. Three different wire speeds are used to study the effect of wire speed on phase transition and residual stress of the silicon wafers. The experimental results indicate that amorphous silicon is generated during resin bonded diamond wire sawing, of which the Raman peaks are at 178.9 cm−1 and 468.5 cm−1. The ratio of the amorphous silicon surface area and the surface area of a single crystal silicon, and the depth of amorphous silicon layer increases with the increasing of wire speed. This indicates that more amorphous silicon is generated. There is both compressive stress and tensile stress on the surface layer of the silicon wafer. The residual tensile stress is between 0 and 200 MPa, and the compressive stress is between 0 and 300 MPa for the experimental results of this paper. Moreover, the residual stress increases with the increase of wire speed, indicating more amorphous silicon generated as well.

Inversion of surface damage and residual stress in ground silicon wafers by laser surface acoustic wave technology

The paper presents a study of surface acoustic waves propagation in a damage layer with finite thickness and residual stress on an orthotropic semi-infinite medium to reveal the application of laser ultrasound in the surface inspection of ground silicon wafers. Biot’s theory of small deformations influenced by initial stress forms the basis for this study. Considering the case that the displacement and boundary forces are continuous at the interface and the forces vanish on the free surface, the required dispersion relation is obtained. We consider a sample of (100) silicon wafer by grinding with fine abrasive grains, which has a machined face with a micrometer-level thickness of surface damage and residual stress. In order to discuss the impact of propagation directions, degree of surface damage, residual compressive stress on the velocity characteristics of surface waves, the numerical computation of the dispersion equations is performed. It has been found that surface damage has a significant effect on the dispersion curve, while the residual compressive stress can only cause a small decrease Δc in the surface wave velocity. The velocity decrease Δc becomes obvious at high frequencies. For a fixed residual compressive stress and frequency, Δc hardly changes with the degree of surface damage and propagation directions. Based on the above characteristics, we study the inverse problem on detecting both surface damage and residual stress simultaneously by SAW velocities and give a corresponding iterative algorithm. This study may provide theoretical guidance for non-destructive testing of residual stress.

Stress Analysis on Ultra Thin Ground Wafers

Grinding wafers is a well established process for thinning wafers down to 100 μm for use in smart cards and stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in Si wafers thinned down to ~20μm by means of an IR time-of-flight like technique. Such aggressive thinning is a requirement for high density vias interconnect, stacked die packaging and flexible electronics. We found that the thinning process used did not add significant stress value on the thinned wafer.

Effect of Surface Oxygen Concentration on Wafer Strength in Floating Zone Si Wafers

The critical stress behavior of low-oxygen-concentration silicon wafers was elucidated by measuring the critical stress of slip generated owing to scratches using the high-temperature three-point bending test method. It is well known that floating zone (FZ) wafers with low oxygen concentrations tend to easily cause slips from dislocation sources such as scratches. The first point observed in the study is that the critical shear stress of FZ wafers had no temperature dependence above 973 K, which may suggest the presence of long-range obstacles for dislocation motion. The second point is that slip generation from scratches was less likely to occur when oxygen atoms were inwardly diffused into the wafer surface by high-temperature thermal treatment. These results will contribute to solving the problem of slip generation from backside scratches, often created during the insulated gate bipolar transistor manufacturing process in which FZ wafers are used.

A bow-free freestanding GaN wafer.

For applications as high-brightness light-emitting-diodes, a bow-free freestanding gallium nitride (GaN) wafer 2 inch in diameter and ∼185 μm in thickness was fabricated by process-designing pit and mirror GaN layers grown via hydride-vapor-phase epitaxy, laser lift-off, N-face polishing of the pit GaN layer, and three-step polishing of the mirror GaN layer using 3.0 μm-, 0.5 μm-, and 50 nm-diameter diamond abrasives and by inductively-coupled-plasma reactive-ion etching. The considerably large concave shape of the GaN wafer could be decreased by controlling the removal amount of the Ga-face mirror layer during the first step of the polishing process, which approached a bow-free shape or changed with further polishing; this well correlated with the residual stress of the polished GaN wafer.

Surface Stress Evolution in Through Silicon Via Wafer During a Backside Thinning Process

During Through Silicon Via (TSV) wafer backside thinning process, excessive surface stress will cause undue warpage or fracture of wafer in subsequent de-bonding step, and further impair the precision of following wafer stacking and packaging. Therefore, it is considerable to investigate the evolution mechanism of wafer stress and how to control it in backside thinning process. Aiming at the above problem, a calculation method is proposed in this paper to characterize surface stress of TSV wafer in a bonding structure, and the method has been confirmed by micro-Raman spectroscopy; Then, based on the method, the change of stress in TSV wafer during a whole backside thinning process is described, and the formation and evolution mechanism of surface stress is analyzed; At last, the stress control performance and corresponding mechanism explanation under different process parameters are demonstrated, and the optimal process condition is selected, which can release more than 80 percent of generated stress. In summary, this work can be regarded as a reference in three-dimension integrated circuit (3D IC) industry to select proper thinning conditions in order to obtain an optimized stress relief performance.

Study of the effect of local photon annealing on stress in silicon wafers

The effect of photon annealing on deformation in the crystal structure of boron doped Cz-Si wafers has been studied using triple crystal X-ray diffraction. Conventional annealing of the entire surface of double-side polished silicon wafers with halogen lamps (photon annealing mode) and rapid thermal annealing produce compression deformation. Annealing with special phototemplate providing for local annealing of multiple separated wafer areas (local photon annealing mode) at relatively low wafer temperatures (less than 55 °C) produces tensile deformation. This effect however is not observed if the reverse side of the annealed wafer contains a mechanical gettering layer. A mechanism explaining the experimental results has been suggested and can be used for the synthesis of charge pumps in photoelectric converter structures.

Formulation of mobile dislocation density in oxygen-precipitated silicon by crystal plasticity model

The relationship between mobile dislocation density and oxygen precipitation characteristics in Czochralski-grown silicon wafers has been investigated using the crystal plasticity model based on an extended Haasen–Alexander–Sumino model in combination with the experimental method. A formula of initial mobile dislocation density for oxygen-precipitated wafers has been deduced from the relationship obtained through the correlation of three-point bending test results and the simulation of a finite element model using the plasticity model. The formula obtained in this work indicates that the size of oxide precipitates has a dominant effect on the strength of precipitated wafers. It is also found from the formulation that the size of oxide precipitates responsible for dislocation slip is larger than about 200 nm, which is consistent with other studies. Analysis of the results also suggests a relationship between upper yield stress and the initial dislocation density which can be used as a tool to predict the yield stress of oxygen-precipitated silicon wafers.

Effect of Macro-scale Mechanical Stress of Silicon Wafer on Room Temperature Photoluminescence Signals

Mechanical stress was applied to single side polished and double side polished Si wafers in polypropylene wafer containers for different localized stress levels and durations. Room temperature photoluminescence (RTPL) spectra from Si wafers were measured before and after applying localized mechanical stress. Significant changes (up to 26% increase) in RTPL intensity were measured from areas under different stress levels even 1 year after the fixtures for mechanical stress generation were removed. Significant effects of localized mechanical stress on RTPL intensity variations were measured up to 49 days after the fixture removal. Nearly fully relaxed RTPL signatures for localized mechanical stress were measured 450 days after the fixture removal. RTPL intensity is found to be very sensitive to the externally applied macro-scale mechanical stress of Si wafers and residual (or memorized) internal stress even after removal of fixtures for external mechanical stress generation.