Surface Stress Evolution in Through Silicon Via Wafer During a Backside Thinning Process

Abstract

During Through Silicon Via (TSV) wafer backside thinning process, excessive surface stress will cause undue warpage or fracture of wafer in subsequent de-bonding step, and further impair the precision of following wafer stacking and packaging. Therefore, it is considerable to investigate the evolution mechanism of wafer stress and how to control it in backside thinning process. Aiming at the above problem, a calculation method is proposed in this paper to characterize surface stress of TSV wafer in a bonding structure, and the method has been confirmed by micro-Raman spectroscopy; Then, based on the method, the change of stress in TSV wafer during a whole backside thinning process is described, and the formation and evolution mechanism of surface stress is analyzed; At last, the stress control performance and corresponding mechanism explanation under different process parameters are demonstrated, and the optimal process condition is selected, which can release more than 80 percent of generated stress. In summary, this work can be regarded as a reference in three-dimension integrated circuit (3D IC) industry to select proper thinning conditions in order to obtain an optimized stress relief performance.