Interconnect Stress Research Articles

Interconnect Stress Testing as a Tool for Assessment of Reliability of Modern PCBs

The of miniaturization can be seen in electronics for some time already. The pinout of active components grows enabling them to have additional functions. The trend in usage of System in a Package (SiP) solutions is also evident thus routing of the active and passive elements became also challenging. To overcome this challenge boards with High Density Interconnection (HDI) where not only through hole, but also different kinds of microvias e.g. blind, buried, stacked, staggered via are used. The standard procedure to test reliability of boards and assemblies is very resource-hungry especially in time and money, as the tests have to be carried out in climatic chambers which lasts for weeks, followed by additional destructive testing like cross-sections. On the other hand IST (Interconnect Stress Testing) is a quick test, that enables to have assessment of the used technology especially the quality of the through holes of all types. Although the coupons are destroyed during the test, it is not necessary to test the manufactured circuits. This saves both materials and time. The technology optimizations and the key findings will be presented within the paper.

Evaluation of bifacial module technologies with combined‐accelerated stress testing

AbstractIn view of the increasing interest and market share of bifacial cells and modules, suitable substrates such as glass and transparent backsheets along with ethylene vinyl acetate (EVA) and polyolefin elastomer (POE) encapsulants were examined in combined‐accelerated stress testing (C‐AST) to evaluate and compare degradation modes. Testing with both monofacial and bifacial cells, we found that glass–glass modules with monofacial cells led to greater grid finger breakage than those with polymeric backsheets. This is attributed to previous X‐ray topography and modeling work showing higher stress in cells and interconnections in glass–glass modules than glass backsheet modules. Consistent with the objectives of C‐AST, which stresses modules at levels corresponding to the limits seen in the natural environment, we observed the UV‐fluorescence signatures of modules tested in C‐AST (considering the degradation associated with developing chromophores, moisture penetration, and photobleaching effects) to be like those in fielded modules, more so than other chamber stress testing implemented for comparison. We found light‐induced degradation (LID) in module types with regenerated (inactive) cells with C‐AST, suggesting the possibility of LID destabilization in some field conditions. We could also distinguish potential‐induced degradation (PID) on the back of the bifacial passivated emitter and rear cells (PERC) in C‐AST. Confirming with ex situ tests, we found polarization‐type PID most prevalent in glass‐glass modules with EVA as would be anticipated considering the greater leakage current through such module encapsulation. Unlike PID tests performed in the dark, which can lead to false positive PID test results, field‐representative illumination is experienced by the modules on the front and back sides while −1200 V system voltage is applied in C‐AST, supporting the conclusion that this module type with glass‐glass construction would be susceptible to PID in the field.

Thermal and Mechanical Characterization of 2.5-D and Fan-Out Chip on Substrate Chip-First and Chip-Last Packages

Heterogeneous integration technology makes possible the integration of multiple separately manufactured components into a single higher level assembly with enhanced functionality and improved operating characteristics. Various types of advanced heterogeneous packages are available, including 2.5-D integrated circuit (IC), fan-out chip on substrate (FOCoS) chip-first, and FOCoS chip-last. This study constructs a nonlinear simulation technique (3-D simulation model) to explore the warpage, extreme low-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> (ELK) interconnect stress, redistribution layer (RDL) trace stress, and board-level solder joint reliability of all three packages. The validity of the simulation model is confirmed by comparing the numerical results for the in-plane dimensional change of an FOCoS chip-last package with the experimental observations over the temperature range of 30 &#x00B0;C&#x2013;260 &#x00B0;C. The thermal performance (i.e., junction-to-ambient thermal resistance) of the three packages is then examined and compared. Finally, <inline-formula> <tex-math notation="LaTeX">$2^{5}$ </tex-math></inline-formula> factorial designs with the analysis of variance (ANOVA) are conducted to examine the effects of the main structural design parameters of the FOCoS chip-last package on its thermomechanical reliability under typical thermal loading conditions. It is shown that a thinner polyimide (PI) layer is beneficial in improving the package reliability by minimizing the coefficient of temperature expansion (CTE) mismatch between the PI layer and the RDL trace, respectively.

Electrical, Thermal, and Mechanical Characterization of eWLB, Fully Molded Fan-Out Package, and Fan-Out Chip Last Package

Fan-out (FO) packages are widely used in handheld, mobile consumer, and Internet of Things (IoT) devices due to the facility they provide for a greater I/O density and the integration of multiple components in a single package. Various types of FO package are available, including embedded wafer-level BGA (eWLB), fully molded (FM), and a flip-chip-based structure referred to as a fan-out chip-last package (FOCLP). In this paper, ANSYS simulations are performed to examine the warpage, extreme low- $k$ (ELK) interconnect stress and board-level solder joint reliability of the various package types. The validity of the simulation model is confirmed by comparing the numerical results for the warpage of the eWLB and FM packages with the experimental observations. Further simulations are then performed to investigate the heat dissipation performance and electrical crosstalk properties of the three packages. Taguchi experiments are conducted to examine the effects of eight control factors [namely, the inclusion (or otherwise) of a backside laminate film, the board thickness, the joint standoff distance, the ball joint diameter, the under bump metallurgy (UBM) diameter, the joint pitch, the die thickness, and the Cu pillar height] on the thermomechanical reliability of the FM package under accelerated thermal cycling testing. Finally, the Taguchi analysis results are used to determine the optimal geometry design of the FM package.

Laser-assisted stress reduction in molybdenum microstructures for CMOS compatible MEMS integration

The fusion of micro-cantilevers over complementary-metal-oxide-semiconductor (CMOS) wafers (with driving electronics) is essential integration requirement for the development of portable sensing devices. In general, the stress gradient in metal cantilevers (after release) lead to structure warping and limits the performance and stability of the final fabricated devices. This work is focused to solve the requirement of (i) having a stress-free metal based micro-electro-mechanical structures (MEMS) without using high-temperature annealing technique and (ii) process compatibility with vapor HF release. We demonstrate a laser-assisted stress controlling scheme to achieve free-hanging metal cantilever without affecting the underneath (essential requirement for CMOS-MEMS integration) deposited layers. The molybdenum (Mo) metal is deposited by physical vapor deposition (PVD) technique at the temperature of 200 °C and then patterned to obtain the microcantilever beams of different length. High-pulse-energy excimer laser (wavelength =248 nm with pulse duration =24 ns) is used to anneal these metal cantilevers and their residual stress is measured by analyzing the final displacement of the released microbeams. Different laser energy density ranging from 200 × 10−3 J/cm2 to 450 × 10−3 J/cm2 is used to study the optimized parameters in the annealing process. Proposed pulsed laser-annealing (PuLA) technique reduces not only the stress gradient but also aid stress-tuning ability that has numerous advantages especially in electrostatic and piezoelectric MEMS devices. Furthermore, we also present the impact of laser action on the grain microstructures and electrical conductivity. Results show that molybdenum microstructures with localized laser heat treatment achieve a reduced surface roughness (from 7.5 nm to 3.8 nm) and improved electrical conductivity. Results demonstrate that the proposed PuLA scheme is a promising technique for (i) eliminating stress in metal interconnects in CMOS-MEMS integrations, (ii) building a stress-free and smooth surface micromechanical platform for N/MEM (resonators, sensors and actuators) devices and (iii) establishing molybdenum as an anti-diffusion barrier in Cu interconnect technology owing to its excellent bulk property.

Failure stress comparison of different pairings of Ag-plating and reflow-oven-processed pressureless-sintered-Ag interconnects

Sintered-silver is a candidate material to supplant solders for interconnects in power electronic packaging for many reasons including its desirably high electrical and thermal conductivities and compliance to Restriction of Hazardous Substances (RoHS) guidelines. The shear failure stress of interconnects though is limited by whatever constituent is the weakest, and that includes any employed plating. In the present study, silver-platings were processed electrolytically, electrolessly, and through sputter deposition and their influence on the entire “interconnect system” shear strength was examined. Test sets employing gold plating and no plating were included for comparison and to aid interpretation. Ambient-air, reflow-oven-processed, pressureless-sintered-silver interconnects were identically fabricated with all plating test sets. It was found that all considered silver-plating methods produced consistently strong (characteristic failure stresses > 55 MPa) sintered-silver interconnects. Because failures tended to be adhesive in all six sets, differences in failure stress among the silver-plated sets and the gold-plated or unplated sets were likely due to differences in the adhesive strength of the sintered silver with silver-plating, gold-plating, or direct bonding with copper.

A Study on Effects of Copper Wrap Specifications on Printed Circuit Board Reliability.

During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.

Analysis of a short beam with application to solder joints: could larger stand-off heights relieve stress?

Physically meaningful and easy-to-use analytical (mathematical) stress model is developed for a short beam with clamped and known-in-advance offset ends. The analysis is limited to elastic deformations. While the classical Timoshenko short-beam theory seeks the beam’s deflection caused by the combined bending and shear deformations for the given loading, an inverse problem is considered here: the lateral force is sought for the given ends offset. In short beams this force is larger than in long beams, since, in order to achieve the given displacement (offset), the applied force has to overcome both bending and shear resistance of the beam. It is envisioned that short beams could adequately mimic the state of stress in solder joint interconnections, including ball-grid-array (BGA) systems, with large, compared to conventional joints, stand-off heights. When the package/printed-circuit-board (PCB) assembly is subjected to the change in temperature, the thermal expansion (contraction) mismatch of the package and the PCB results in an easily predictable relative displacement (offset) of the ends of the solder joint. This offset can be determined from the known external thermal mismatch strain (determined as the product of the difference in the coefficients of thermal expansion and the change in temperature) and the position of the joint with respect to the mid-cross-section of the assembly. The maximum normal and shearing stresses could be viewed as suitable criteria of the beam’s (joint’s) material long-term reliability. It is shown that these stresses can be brought down by employing beam-like joints, i.e., joints with an increased stand-off height compared to conventional joints. It is imperative, of course, that, if such joints are employed, there is still enough interfacial real estate, so that the BGA bonding strength is not compromised. On the other hand, owing to the lower stress level, reliability assurance might be much less of a challenge than in the case of conventional joint configuration. By employing beam-like solder joints one can even manage to avoid inelastic deformations of the joints, thereby increasing dramatically their fatigue lifetime. Future work will include, but might not be limited to, the finite-element computations, experimental evaluations (such as, e.g., shear-off testing), and analyses of the occurrence and the role of the inelastic strains, if any. The paper is intended for materials-, reliability- and industrial- physicists and applied scientists.

Reliability of High Temperature Laminates

Printed circuit boards have been reported to have limited lifetime at 200 to 250°C. Characterization of high temperature laminates for application at 200 to 250°C was conducted to better quantify their lifetime using accelerated testing of key functional parameters. Eight high temperature laminates consisting of 3 material types was evaluated. Life testing was applied for via cyclic life, weight loss, peel strength, and surface insulation resistance. Via lifetime was characterization using Interconnect Stress Test (IST) coupons. Weight loss was measured at intervals during the life of the tests. Peel strength was tested using IPC IPC-TM-650 method 2.4.8c. Weight loss was characterized using isothermal aging. Comparison of lifetime is made between the laminate samples. The non-polyimide laminates exhibited the longer life times than polyimide laminates in most tests except peel strength. Peel strength is the life limiting parameter for the laminates. Parylene HT was found to improve stability in peel strength and weight loss of one PTFE laminate tested.

Effect of alloy seed on Cu interconnect electromigration and stress migration

Effect of alloy seed on electromigration (EM) and stress migration (SM) has been analyzed based on Cu-based, dual-damascene technologies. It is found that the thickness of aluminium (Al) seed layer has strong impact on metal resistance, EM lifetime and SM performance. Thicker Al seed layer can induce higher metal resistance, improve EM lifetime better and bring more apparent negative shift of resistance during SM.

Electron fluence driven, Cu catalyzed, interface breakdown mechanism for BEOL low-k time dependent dielectric breakdown

During technology development, the study of low-k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low-k TDDB are closely correlated with the leakage conduction mechanism of low-k dielectrics. In addition, low-k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low-k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low-k breakdown model. Then we review several other low-k TDDB models that consider only intrinsic low-k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low-k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low-k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low-k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.

Microstructure-based multiphysics modeling for semiconductor integration and packaging

Semiconductor technology and packaging is advancing rapidly toward system integration where the packaging is co-designed and co-manufactured along with the wafer fabrication. However, materials issues, in particular the mesoscale microstructure, have to date been excluded from the integrated product design cycle of electronic packaging due to the myriad of materials used and the complex nature of the material phenomena that require a multiphysics approach to describe. In the context of the materials genome initiative, we present an overview of a series of studies that aim to establish the linkages between the material microstructure and its responses by considering the multiple perspectives of the various multiphysics fields. The microstructure was predicted using thermodynamic calculations, sharp interface kinetic models, phase field, and phase field crystal modeling techniques. Based on the predicted mesoscale microstructure, linear elastic mechanical analyses and electromigration simulations on the ultrafine interconnects were performed. The microstructural index extracted by a method based on singular value decomposition exhibits a monotonous decrease with an increase in the interconnect size. An artificial neural network-based fitting revealed a nonlinear relationship between the microstructure index and the average von Mises stress in the ultrafine interconnects. Future work to address the randomness of microstructure and the resulting scatter in the reliability is discussed in this study.

High Temperature Laminate Characterization

Printed circuit boards have been reported to have limited lifetime at 200 to 250°C. Characterization and modeling high temperature laminates for application at 200 to 250°C was conducted to better quantify the mean lifetime using accelerated testing of key functional parameters. Life testing and model development was applied for via cyclic life, peel strength, and weight loss. Four high temperature laminates consisting of 2 types were evaluated. Via lifetime was characterization using Interconnect Stress Test (IST) coupons. Peel strength was tested using IPC IPC-TM-650 method 2.4.8c. Weight loss was characterized using isothermal aging. Comparison of lifetime is made between the laminate samples.

Finite element analysis of thermal stress for different Cu interconnects structure

Thermal stress behavior of various Cu/low-k dual damascene Cu interconnects structure is investigated in this article. Finite element analysis software ANSYS is applied to simulate the thermal stress distribution in the Cu interconnects with stress control layer (SCL), to identify the thermal stress of Cu interconnects with via gouging different depth into the underlying metal M1 and to study the thermal stress of Cu interconnects with dielectric slot. The simulation results conclude that the thermal stress of Cu interconnects is reduced by introducing stress control layer (SCL) between metal-level inter-layer dielectric (ILD) film and via-level ILD film. The thermal stress at the interface of Cu/via decreases with increasing via gouging depth, so void nucleation sites appear in Cu line M1, away from via. Cu line with dielectric slot has lower hydrostatic stress at the Cu cap/via interface than that without dielectric slot.

Thermomechanical Design for Fine Pitch 3D-IC Packages

Low stress package design is one of the greatest challenges for the realization of reliable 3D integrated devices, since they are composed of elements susceptible to failures under high stress such as thin dies, metal through silicon vias (TSVs), and fine pitch interconnections. In variety of package components, an organic interposer is a key to obtain low cost modules with high density I/Os. However, the large mismatch in coefficient of thermal expansion (CTE) between silicon dies and organic laminates causes high stress in an organic package. The major parametric components in 3D devices are dies with /without Cu-TSVs, laminates, bumps, and underfill layers. Especially, the die thicknesses and underfill properties are ones of the parameters that give us some range to control as package design parameters. In general, the underfill material with a high modulus and a low CTE is effective in reducing the stress in solder interconnections between the Si die and the laminate. However, the filler content of underfill materials with such mechanical properties generally results in high viscosity. The use of high viscous materials in between silicon dies in 3D modules can degrade process ability in 3D integration. In this study, we show that the interchip underfills in 3D modules have a wider mechanical property window than in 2D modules even with fine pitch interconnections consisting mostly of intermetallic compounds (IMCs). Also the finite element analysis results show that the optimization of the structural or thermomechanical properties of organic laminates and interchip underfill contributes to reduction of stressing thinned silicon dies which may have some risks to the device performance.

Correlating Interconnect Stress Test and Accelerated Thermal Cycling for Accessing the Reliabilities of High Performance Printed Circuit Boards

Understanding the failure mechanism of a plated through hole (PTH) is essential for a complete picture of their life span, and hence for the continued electronic reliability prediction and development of high performance printed circuit boards. This paper presents the efficacy of establishing a correlation between interconnect stress test (IST) and accelerated thermal cycling (ATC) data on standard high performance coupons. In accord with the observation in PTH micro-sectioning, a PTH failure mechanism is proposed based on the thermal expansion-induced shearing at the copper-resin interface. The PTH cycle to failure data from the two methodologies, IST and ATC, are correlated. In terms of the glass transition temperature, a linear relationship exists between two different data sets. It is also demonstrated that the base material thermal property and PTH sizes are the two essential factors determining the reliability of a PTH. Furthermore, a life stress model is created to predict the life time of a coupon at a particular temperature level.

Finite element simulation of hydrostatic stress in copper interconnects

This work focuses on numerical modeling of hydrostatic stress, which is critical to the formation of stress-induced voiding (SIV) in copper damascene interconnects. Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry. In addition, hydrostatic stress is studied through the influences of different low-k dielectrics, barrier layers and line widths of copper lines, and the results indicate that hydrostatic stress is strongly dependent on these factors. Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.

Self-consistent design issues for high frequency Cu interconnect reliability incorporating skin effect

This paper presents a self-consistent method to guide high frequency reliability design for a two-level Cu interconnect structure, incorporating the impact of skin effect. A skin-effect-related parameter “Effective Cross Section Area” is introduced to make a more precise prediction of interconnects’ thermal profile due to self-heating. Since via and contact interfaces in Cu interconnects are at the highest risk of failure, via temperature is used to calculate the interconnect stress evolution and lifetime. From the research of the interconnect structure stressed by a type of arbitrary rectangular alternating current, we notice that the direction of the average current must be taken into account, while that consideration is not involved in self-consistent design for Al interconnects. We also found that generally, temperature, current density/intensity, frequency, and duty cycle are four specifications that restrict one another in high frequency interconnect reliability design, and if one increases, interconnects’ tolerance of the other three will decrease.

The effect of stress migration on electromigration in dual damascene copper interconnects

Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to stress migration (SM) and electromigration (EM). At use condition, these two failure mechanisms play a collective role in causing interconnect failure. We present a study on SM and EM interaction in lower (MX structure) and upper metal (MX+1 structure) of dual-damascene Cu/low-κ interconnects. It is found that both mechanisms are dependent; statistical analysis shows that EM failure time is affected by the presence of residual stress induced by SM. This effect was more severe in the lower metal, where the EM median-time-to-failure (t50) for the majority of samples could be degraded by 30%–60%. For the upper metal of Cu interconnects, the t50 is degraded by about 10%. The reliability implication of the residual stress in copper interconnects on the EM is further investigated with various failure analysis techniques and three-dimensional finite element simulation. It is proposed that SM can influence EM when there is significant amount of vacancy accumulation due to SM in the cathode area which accelerates EM nucleation time. In the case of the MX structure, our experimental results show that SM and EM interaction occurs exactly below the via at the MX cathode side, leading to abrupt failures. On the other hand, in MX+1 structure, vacancies are likely to accumulate at the edge of upper metal lead during SM test, thus accelerating the failure during subsequent EM test. A failure mechanism model for stress evolution and void formation is proposed to provide insight into the interaction between these two failure mechanisms.

Electro-Thermo-Mechanical Characterizations of Various Wire Bonding Interconnects Illuminated by an Electromagnetic Pulse

A comprehensive electro-thermo-mechanical transient investigation is carried out to characterize time-dependent thermal and mechanical responses of metal wire bonding interconnects, as they suffer from the impact of an electromagnetic pulse (EMP) with different current or voltage waveforms. In our mathematical implementation, a hybrid time-domain finite element method is applied to simulate mutual interactions among electrical, thermal, and mechanical fields, with all nonlinearities of temperature-dependent electrical conductivities, thermal conductivities, thermal expansion coefficients, and even the Young's modulus of materials being treated appropriately. The developed algorithm is partially validated by computing transient temperature and thermal stress of other interconnects with good agreement with reference results. Parametric studies are performed to show the effects of EMP waveform parameters, geometrical and physical parameters of various wire bonding interconnects on their transient thermal and mechanical responses, thus providing basic information for their electromagnetic protection so as to suppress the impact of an intentional EMP.