Strained Silicon-on-insulator Research Articles

Strained Silicon-on-Insulator Platform for Cointegration of Logic and RF—Part I: Implant-Induced Strain Relaxation

The relaxation of tensile strain in fully depleted (FD) strained silicon-on-insulator (SSOI) by means of ion implantation is experimentally demonstrated in this work. This could enable SiGe p-channel field-effect transistors (pFETs) with high compressive strain (after ion implantation and Ge condensation) to be formed together with Si n-channel field-effect transistors (nFETs) with high tensile strain on the same substrate. From simulations in advanced technology node, 0.8% strain of nFETs and −0.9% strain of pFETs in fin structures can provide saturation drain current and peak ${G}_{\text {m}}$ enhancements of ~20%–30%. ${f}_{\text {T}}$ and ${f}_{\text {max}}$ benefit greatly from strain across the entire range of ${V}_{\text {G}}$ , with their peak values increasing significantly, thus allowing SSOI devices to meet 5G targets. In addition, forward back-bias shifts ${f}_{\text {T}}$ and ${f}_{\text {max}}$ curves toward lower $\boldsymbol \vert {V}_{\text {G}}\boldsymbol \vert $ , enabling reduced power consumption at the same high performance and providing better linearity. Hence, the ability to form highly strained nFETs and pFETs together on a common FD-SSOI substrate paves the way for it to become the ultimate high-performance complementary metal-oxide-semiconductor (CMOS) platform for 5G RF and logic circuits. The relaxation of the tensile strain is demonstrated and documented in Part I. A novel Comb-like device architecture to further enhance the SSOI electrical and RF performance is provided in Part II.

Highly Scaled Strained Silicon-On-Insulator Technology for the 5G Era: Impact of Geometry and Annealing on Strain Retention and Device Performance of nMOSFETs

Strained silicon-on-insulator (SSOI) is a promising platform for 5G, which will require both high-performance and low-power complementary metal–oxide–semiconductor (CMOS) devices. Hence, it is important to understand the behavior of strain in SSOI at deeply scaled dimensions. We thus present a simulation study of SSOI technology, where the strain profiles of “fins” with different dimensions and layer thicknesses are analyzed. We discover, for the first time, that a buried oxide (BOX) as thin as 10–15 nm is able to effectively memorize the strain. It is also able to retain the strain under annealing up to 1000 °C, a result verified by the Raman measurements. Such a thin BOX enables a good back-gate control for dynamic threshold voltage ( ${V}_{\text{t}}$ ) tuning of SSOI transistors. The ability to have a good performance enhancement (from strain), and dynamic ${V}_{\text{t}}$ tunability (from thin BOX) makes SSOI favorable for 5G mixed-signal applications.

The formation mechanism of globally biaxial strain in He+ implanted silicon-on-insulator wafer based on the plastic deformation and smooth sliding of buried SiO2 film

In this paper, we proposed an approach to obtain a globally biaxially strained silicon-on-insulator (SOI) wafer, and the strain mechanism was discussed. By this process, both biaxially tensile and compressive strained SOI (sSOI) can be obtained. The strain introduced into the SOI layer is mainly contributed by the plastic deformation of the buried SiO2 film caused by annealing with the deposition of a high-stress SiN film. Furthermore, He+ implantation at the interface between SiO2 and the substrate Si layer is confirmed to effectively enhance the strain by the sliding of the buried SiO2 at the SiO2-substrate Si interface. Raman spectroscopy shows that the strain of the He+ implanted sSOI has a significant enhancement of more than 300% compared with the unimplanted sSOI.

Nanomechanical Properties of Germanium-on-Insulator (GeOI) Films

Silicon-on-insulator (SOI) is envisaged as a better alternative to bulk silicon due to its superb performance and less power consumption. The fabrication of the silicon-on-insulator (SOI) and strained silicon-on-insulator (SSOI) is accomplished using wafer bonding and the SMART CUT layer splitting technology for film exfoliation. Strained SOI (SSOI) substrates are specifically developed with SiGe straining layers for high mobility channel devices [1-3]. The fabrication of Germanium-on-Insulator (GeOI) proved to be the best choice material for Si-based photodetection. Ge possesses a strong linear absorption of up to 1.55 µm, a strong compatibility with Si CMOS process, and direct energy bandgap of 0.8 eV [4]. Also, Ge retains higher carrier mobility as compared to Si, which promises faster operation. Although the lattice mismatch parameter between Ge and Si is large i.e., 4.2%, epitaxial growth of high quality Ge thick films on Si can be accomplished. GeOI films of 100, 220, 250, and 290 nm thick were fabricated using wafer bonding and Smart Cut technology. The structural and surface properties were explored using field emission scanning electron (FE-SEM) and atomic force microscopy (AFM). The crystal structure and orientation of the films were examined using X-ray diffraction. The GeOI film thickness was verified using field emission scanning electron microscopy (FESEM) in cross-section as shown in Figure 1. The nanomechanical properties were measured using nanoindentation to determine the modulus and hardness of the GeOI films. Constant displacement indentations in CSM mode of 10% of the film thickness, to circumvent the substrate effects were performed on each film to study the film properties. References Mazure and A.J. Auberton-Herve, Proc. of 35th European Solid-State Device Research Conf. ESSDERC, p. 29 (2005)A. Langdo, M. T. Currie, Z.-Y. Cheng, J.G. Fiorenza, M. Erdtmann, G. Braithwaite, C.W. Leitz, C.J. Vineis, J. A. Carlin, A. Lochtefeld, M. T. Bulsara, I. Lauer, D.A. Antoniadis, M. Somerville, Solid-State Electronics, 48 , 1357 (2004).I. Cayrefourcq, A. Boussagol and G. Celler, in SiGe and Ge: Materials, Processing, and Devices, ECS Trans. 3, (7), 399 (2006) Figure 1

Fin shape dependent variability for strained SOI FinFETs

In this paper, for the first time impact of fin shape variation on 22-nm technology node strained silicon-on-insulator (SSOI) n-FinFET has been examined. With 3D-TCAD simulator, the electrical characteristics are analyzed and compared for devices with fin shapes, rectangular and triangular. Here, strained technique improved the driving current and reduction in leakage current is done through use of triangular fin shape devices. For the same bottom width, triangular FinFETs improved OFF current ~ 2–2.5×. Moreover, the device characteristics variability has been considered through variations in fin width and work function (WF). It observed that triangular FinFETs with lightly doped fins are more susceptible for short channel effects. Due to low leakage current triangular FinFETs can maintain suitable ON to OFF ratio under the circumstance of work function and fin width variation.

High-resolution X-ray microdiffraction from a locally strained SOI with a width of 150 nm

150-nm-wide region in a locally strained silicon on insulator (SOI) was studied using high-resolution X-ray microdiffraction technique. Synchrotron radiation X-rays with energies of 10 keV were focused on the sample by a zone plate. The focused beam size was approximately 0.8 × 0.4 μm2. The sample was a model of a gate of metal-oxide semiconductor field-effect-transistors (MOSFETs); a 30-nm-thick SOI plate with an 80-nm-thick silicon nitride capping film with tensile inner stress. The capping film was removed in a stripe pattern by etching with a width of 150 nm. The width of the gap where the film is removed corresponds to the gate length of MOSFETs. Using thin SOI as a sample, we could observe only thin surface area even by X-ray diffraction that has deep penetration depth. Reciprocal space maps (RSMs) of symmetrical SOI 004 were measured around the 150-nm-gap of the film. RSMs showed that the SOI lattice was tilted along the stripe pattern up-to 0.1 deg at both sides of the gap. The tilting spreads more than 1 μm distant from the center of the gap.

Experimental Investigation on Alloy Scattering in sSi/${\rm Si}_{0.5}{\rm Ge}_{0.5}$/sSOI Quantum-Well p-MOSFET

Alloy scattering in a sSi/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Si}_{0.5}{\rm Ge}_{0.5}$</tex> </formula> /strained Silicon on Insulator (SOI) (sSOI) quantum-well (QW) p-MOSFET is investigated by hole density modulation through applying back-gate biases. The hole mobility under negative back-gate biases is found degraded by intensified alloy scattering at low electrical field because more holes are distributed in the bulk <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Si}_{0.5}{\rm Ge}_{0.5}$</tex></formula> . At higher electrical field, the higher density of holes populated at the Si/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Si}_{0.5}{\rm Ge}_{0.5}$</tex> </formula> .interface and less holes in the bulk <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Si}_{0.5}{\rm Ge}_{0.5}$</tex> </formula> .result in less pronounced alloy scattering, leading to mobility enhancement under negative back-gate biases. This confirms experimentally that alloy scattering does not play a significant role in the hole mobility of sSi/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Si}_{0.5}{\rm Ge}_{0.5}$</tex></formula> /sSOI QW p-MOSFETs under normal operating mode.

X-Ray Photoemission Study of SiO&lt;sub&gt;2&lt;/sub&gt;/Si/Si&lt;sub&gt;0.55&lt;/sub&gt;Ge&lt;sub&gt;0.45&lt;/sub&gt;/Si Heterostructures

An SiO2/Si-cap/Si0.55Ge0.45 heterostructure was fabricated on p-type Si(100) and strained silicon on insulator (SOI) substrates by low pressure chemical vapor deposition (LPCVD) and subsequent thermal oxidation in an O2 + H2 gas mixture. Chemical bonding features and valence band offsets in the heterostructures were evaluated by using high-resolution x-ray photoelectron spectroscopy (XPS) measurements and thinning the stack layers with a wet chemical solution.

Experimental Investigation of Hole Transport in Strained $\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{SOI}$ pMOSFETs—Part I: Scattering Mechanisms in Long-Channel Devices

This paper presents a wide experimental study of hole transport in SiGe pMOSFETs. Various Ge contents, from 20% up to 60%, and growth templates [unstrained or tensely strained silicon-on-insulator (SOI)] were screened in order to study the influence of various strain levels and Ge concentrations. Electrical results have been compared with the amount of strain in the channel, characterized through dark-field electron holography and nano-beam electron diffraction. The SiGe channel/oxide interface has been investigated through spectroscopic charge pumping and low temperature measurements. We found the signature of Ge-induced defects, particularly near the valence band. The different scattering mechanisms limiting the hole mobility in long-channel transistors have been decorrelated and discussed in the light of the different experimental data provided. We have shown in particular the low contribution of alloy scattering in the SiGe devices under study, and that carrier transport is dominated by the strain effect for Ge content up to 40%. The roughness parameters of the SiGe channel/oxide interface are also modified, with a less prejudicial impact on mobility. The effect of strain and Ge content on the different scattering mechanisms has been established. The combination of all the scattering contributions leads to a maximum mobility at room temperature for a Ge content <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ge</sub> = 0.4 on an SOI template, or equivalently, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ge</sub> = 0.6 on a strained SOI template.

Strain Nano-Engineering: SSOI as a Playground

Ultrathin strained silicon-on-insulator (SSOI) has been in the limelight of device scientists and engineers as one of the materials that can possibly extend the lifetime of the current silicon technology. In this paper, we show that, beyond this technological interest, SSOI also provides a rich platform to explore and explain a number of fundamental phenomena. In particular, ultrathin SSOI substrates are exploited to elucidate basic nanomechanical properties of silicon. Particularly, the bending associated with free surface-induced relaxation upon nanoscale patterning are investigated using micro-Raman scattering, high resolution transmission electron microscopy, and nano-beam electron diffraction. The observed morphological changes in SSOI nanostructures cannot be explained by the classical Stoney's formula or related formulations developed for nanoscale thin films. Instead, a continuum mechanical approach is employed to describe these observations through three-dimensional numerical calculations of relaxation-induced lattice displacements. The use of SSOI to implement novel nanoscale devices is also discussed.

Strain Stability in Nanoscale Patterned Strained Silicon-On-Insulator

Nowadays, strain engineering plays a key role in boosting the performance of Si-based nanoelectronics. So far a tremendous progress has been made in establishing methods for strain manipulation in Si nanodevices. This has brought up further challenges in terms of development of reliable probes to characterize the strain on the nanoscale. In this paper, we discuss strain imaging using multi-wavelength micro-Raman spectroscopy. As a model system, we investigate the strain behavior upon nanoscale patterning of ultrathin strained silicon-on-insulator (SSOI). We show that valuable details on the strain depth distribution can be obtained by combining deep UV and visible Raman microprobes. Additionally, we also demonstrate that strain mapping with high lateral resolution can be achieved using UV-Raman with glycerin-immersed high numerical aperture objective lens. Results from nano-beam electron diffraction and peak-pairs analysis of high-angle annular dark field images are also presented. Detailed 3D finite element simulations of edge-induced strain relaxation in SSOI nanostructures augment our experimental studies.

Multiwavelength micro-Raman analysis of strain in nanopatterned ultrathin strained silicon-on-insulator

We developed a heterostructure to assess accurately the strain evolution upon nanopatterning of 15 nm thick tensile strained silicon-on-insulator (SSOI). Here the long-standing concern of substrate background in micro-Raman analysis was circumvented by the introduction of a Ge layer underneath the buried oxide. Unprecedented insights into the strain behavior in SSOI nanostructures were obtained by combining deep UV and visible micro-Raman probes. We found that the formation of edges results in a strong relaxation near the surface parallel to an increase in the strain at the Si/oxide interface. This disparity in the strain evolution between surface and interface leads to the coexistence of compressive and tensile strained regions within the same structure at a lateral dimension of 50 nm. This heterogeneous distribution of strain should be taken into account in the design and fabrication of SSOI-based nanodevices.

Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon

Ultrathin Ni silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained SOI (SSOI) substrates. The Ni layer thickness crucially determines the silicide phase formation: With a 3-nm Ni layer, high-quality epitaxial NiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers were grown at temperatures > 450°C, while NiSi was formed with a 5-nm-thick Ni layer. A very thin Pt interlayer, to incorporate Pt into NiSi, improves the thermal stability and the interface roughness and lowers the contact resistivity. The contact resistivity of epitaxial NiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is about one order of magnitude lower than that of a NiSi layer on both As- and B-doped SOI and SSOI.

The Impact of Oxide Traps Induced by SOI Thickness on Reliability of Fully Silicide Metal-Gate Strained SOI MOSFET

In this letter, we investigate the effects of oxide traps induced by various silicon-on-insulator (SOI) thicknesses ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOI</sub> ) on the performance and reliability of a strained SOI MOSFET with SiN-capped contact etch stop layer (CESL). Compared to the thicker <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOI</sub> device, the thinner <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOI</sub> device with high-strain CESL possesses a higher interface trap ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) density, leading to degradation in the device performance. On the other hand, however, the thicker <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOI</sub> device reveals inferior gate oxide reliability. From low-frequency noise analysis, we found that thicker <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOI</sub> has a higher bulk oxide trap ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BOT</sub> ) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior TDDB reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOI</sub> devices in this strain technology.

Strain Stability and Carrier Mobility Enhancement in Strained Si on Relaxed SiGe-on-Insulator

A low thermal budget process to fabricate strained Si metal-oxide-semiconductor field-effect transistors (MOSFETs) on a strain-relaxed silicon–germanium-on-insulator (SGOI) by strain engineering is described. The strain stability in the top strained Si is studied after low temperature oxidation, ion implantation, and rapid thermal annealing, and only 7–9% relaxation is observed. The Ge content distribution in a strained-silicon-on-insulator (SOI) is investigated to validate the process with a low thermal budget. Ge, reaching the strained interface, inevitably degrades the gate oxide properties. The electron and hole mobility values in the biaxial strained-SOI are investigated and compared to those in MOSFETs fabricated in strain-relaxed SGOI and SOI substrates. Both carrier mobilities are enhanced, and the process is much simpler than using uniaxial strained Si. The relaxed-SGOI MOSFETs possess the lowest carrier mobility, and both the electron and hole mobility values in the strained-SOI MOSFETs are enhanced compared to the devices fabricated in the control samples and bulk Si. The SiGe layer in strained-SOI can lead to a larger leakage current.

Silicon nanowire FETs with uniaxial tensile strain

We present experimental results on on-current and transconductance gain and mobility enhancement in Si nanowire FETs (NW-FETs) fabricated on silicon-on-insulator (SOI) and biaxially tensile strained SOI (SSOI). The Si NW-FETs show very high I on / I off -ratios of 10 7 and off-currents as low as 10 - 13 A . Inverse sub-threshold slopes of about 80 mV/dec for SOI n- and p-FETs and 65 mV/dec for strained SOI n-FETs were obtained. The on-current and transconductance of Si NW-nFETs fabricated on strained SOI substrates are 2.5 and 2.1 times larger, respectively, compared to identical devices on SOI due to uniaxial tensile strain along the wires. An electron mobility enhancement by a factor of 2.3 in uniaxial tensile strained NW-FETs was found. Moreover, the on-currents of n- and p-NW-FET are more symmetrical compared to planar devices, differing only by a factor of 1.6, for 〈 1 1 0 〉 NW channel direction on a (1 0 0) wafer.

Measurement of effective electron mass in biaxial tensile strained silicon on insulator

We present measurements of the effective electron mass in biaxial tensile strained silicon on insulator (SSOI) material with 1.2 GPa stress and in unstrained SOI. Hall-bar metal oxide semiconductor field effect transistors on 60 nm SSOI and SOI were fabricated and Shubnikov–de Haas oscillations in the temperature range of T=0.4–4 K for magnetic fields of B=0–10 T were measured. The effective electron mass in SSOI and SOI samples was determined as mt=(0.20±0.01)m0. This result is in excellent agreement with first-principles calculations of the effective electron mass in the presence of strain.

Agglomeration process in thin silicon-, strained silicon-, and silicon germanium-on-insulator substrates

In this paper we present a comparative study of the agglomeration process in silicon-on-insulator (SOI), silicon germanium-om-insulator (SGOI), and strained SOI (SSOI) thin layers under thermal annealing in ultrahigh vacuum. In particular, we provide the first evidence and characterization of agglomeration in SGOI and SSOI substrates. A common agglomeration dynamics is observed in all the substrates investigated, with the semiconductor-on-insulator layer thickness being the main parameter governing it. These findings provide a better understanding of the surface-energy-driven dewetting phenomenon in semiconductor layers and allow us to single out the influence of the surface and stress energies on the void formation and evolution, as well as on the size and density of the agglomerated islands.

Effect of Device Parameters on the Breakdown Voltage of Impact-Ionization Metal–Oxide–Semiconductor Devices

The effect of device parameters on the breakdown voltage of impact-ionization metal–oxide–semiconductor (I-MOS) devices has been investigated. In order to realize I-MOS devices with sufficiently low breakdown voltage, we examined the downscaling of the device size and the introduction of narrow-bandgap material by using device simulation. The downscaling of the device size included the reduction of i-region length (LI), source extension junction depth (xj,se) and gate oxide thickness (tox). However, the acceptable breakdown voltage (<-5 V) could not be achieved. Thus, narrow-bandgap material is necessary in addition to device scaling. A strained silicon-on-insulator (SSOI) substrate with sufficient bandgap reduction will meet the demands.

Strained Silicon on Wafer Level by Waferbonding: Materials Processing, Strain Measurements and Strain Relaxation

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or compressive strain in the channel region of MOSFETs. Biaxial strain is introduced by growing of thin silicon layers on SiGe buffers and their transfer to oxidized silicon substrates. The latter forms strained silicon on insulator (SSOI) wafers characterized by tensile strain only. Future CMOS device technologies require the combination of the global strain of SSOI substrates with local stressors to increase the device performance.