Strained SiGe Channel Research Articles

(Keynote) Group-IV Epitaxy and Process Solutions for Stacked Gate-All-Around Nanosheet Technology Performance Improvement

Stacked gate-all-around (GAA) nanosheet (NS) devices are attractive candidates to replace FinFETs at the 3nm technology node and beyond due to their excellent electrostatic properties and scalability. GAA NS technology has multiple advantages compared to FinFET technology. GAA NS device with stacked nanosheets offers increased drive current compared to FinFET technology due to significant improvement in the total effective width per active footprint GAA NS device also enables gate length scaling thanks to its outstanding electrostatics and short channel control. Unlike FinFET, the active footprint is not quantized on NS. Therefore, flexible power/performance tuning can be achieved with variable nanosheet width. The industry agrees that GAA NS structure is the architecture of choice for the next device structure after FinFET as scaling continues. In fact, mass manufacturing for stacked GAA Nanosheet technology started and is currently offered as first-generation product at the 3nm technology node.Fabricating GAA NS structure can take advantage of many of the FinFET process integrations by adding elemental technology modules unique to the GAA NS structure. A specific SiGe/Si multi-layer epitaxy is employed for stacking Si NS channels. The SiGe layer is used as a sacrificial layer for forming inner spacer (IS) and defining the suspension thickness, the distance separating two consecutive stacked Si NS channels. The uniformity and crystallinity for the epitaxial SiGe/Si layers within wafer is critical since it will determine the Si NS channel thickness and performance. Abrupt Ge profile at the SiGe/Si interface is also required for achieving selective SiGe removal to form optimal IS profile and suppress Si NS channel surface roughness post channel release. IS is necessary to isolate the gate and S/D, playing an important role as a physical barrier to prevent S/D damage during channel release while providing device benefits. The IS profile and thickness are important for tuning device performance by modulation of capacitance and resistance. S/D epitaxial growth becomes more difficult as devices are scaled with a reduction of the opening of the S/D region For a GAA NS structure employing IS, all the focus will be on improving the integration and process to avoid negatively impacting the subsequent S/D epitaxial growth.PFET device performance degradation is expected due to modulation of hole mobility. Transitioning the device structure from FinFET to GAA NS dramatically changes the transport properties as the channel surface orientation changes and is more dominated by the (110) surface compared to (001) plane for a FinFET. Therefore, exploring performance improvement techniques is required for next generation GAA CMOS technologies in order to improve the pFET device. Increasing channel carrier mobility is one way to improve device performance. Hole mobility can be increased by inducing compressive stress into the channel material. SiGe is one of the most promising materials for pFET channel as strained SiGe channel FinFET device shows intrinsic mobility gain compared to Si channel FinFET. Additional SiGe channel benefits include Vt tunability and superior NBTI performance. As such, applying SiGe channel into GAA NS device has great potential for further improving pFET device performance. SiGe cladded NS channel formation through selective SiGe epitaxial growth post Si channel release is an effective method for maintaining strain in the SiGe region. The lattice constant difference between the epitaxial SiGe layer and Si channel NS results in compressive strain in the SiGe cladded layer. This technique maintains the compressive strain since there is no patterning step in the downstream process. Altering the channel orientation is another technique for modulating carrier mobility independent of internal and external stressor elements. For instance, hole mobility is higher for (110) planes than for (001) planes. The same process integration can be utilized for both substrate types for fabricating GAA Si channel NS devices on (001) and (110) bulk substrates, although careful engineering is required for SiGe/Si epitaxy on (110) substrate.In this talk, we will review the epitaxy processes and related technologies for GAA NS device fabrication. In addition, performance enhancement techniques such as, (1) strained SiGe channel and (2) channel surface orientation with high hole mobility, that can be applied for GAA NS pFET device are discussed.

High performance junctionless FDSOI SiGe channel p-FinFET with high ION/IOFF ratio and excellent SS

This paper presents a novel FDSOI FinFETs with SiGe channel/Si cap layer (35 nm/5 nm) formed on SOI wafers with 20 nm Si body. Electrical characterization result shows that JL FDSOI FinFETs with SiGe channel exhibited low subthreshold slope (SS) of 86 mV/decade and record high ON-OFF current ratio (ION/IOFF = 2 × 106) at VD = -0.5V, respectively. Device performance improvement was mainly attributed to high-epitaxial quality compressive strained SiGe channel and novel device structure. The strain in the channel of the transistors was estimated locally in TEM using Nano beam diffraction (NBD) technique. The FDSOI FinFET with SiGe channel, lays the foundation for the further development of high speed, high density, low cost, and 3D monolithic integration circuits.

Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness

Compressively strained SiGe is an interesting channel material for sub 45 nm p-MOSFETs because of its superior hole mobility (up to 10x over bulk Si channels) and compatibility with current Si manufacturing technologies. In this work, the impact of heterostructure composition and SiGe channel thickness on the electrical characteristics of p-MOSFET are studied. Using strained Si0.8Ge0.2 p-MOSFET, the thickness was altered to a few thicknesses of 3 nm, 5 nm, 7 nm, and 9 nm respectively. The optimal thickness was then used for Ge compositions (x = 0.2). The project was realized utilizing computer-aided Silvaco TCAD tools, with ATHENA tools creating the p-MOSFET structure and ATLAS tools doing the device simulation. The strained-Si1-xGex p-MOSFET and the Si p-MOSFET were compared in terms of their performances. The ID-VG and ID-VD characteristics, as well as the threshold voltage, VTH extraction, were the focus of the device simulation. The 7 nm thickness strained-Si0.8Ge0.2 p-MOSFET exhibited lower VTH than other SiGe thicknesses and the Si p-MOSFET which is VTH = 0.074 V. The lower threshold voltage of the strained-Si0.8Ge0.2 with 7 nm thickness indicating that the strained-Si1-xGex contributed to the decreased power consumption. In addition, the extracted IDsat for the strained-Si0.8Ge0.2 p-MOSFET with 7nm thickness provided higher IDsat compared to conventional Si p-MOSFET and other SiGe thicknesses devices. As compared to Si p-MOSFETs, the output characteristics of the strained-Si1-xGex demonstrated a drain current improvement by a factor of 1.01.

Design and optimization of stress/strain in GAA nanosheet FETs for improved FOMs at sub-7 nm nodes

Stress/strain engineering techniques are employed to boost the performance of Gate-all-around (GAA) vertically stacked nanosheet field-effect transistors (NSFETs) for 7 nm technology nodes and beyond. In this work, we report on the 3D numerical simulation study of the impacts of source/drain epitaxial and uniaxial strained-SiGe channel stresses on p-type NSFETs. It is shown that the uniaxial strained-SiGe channel improves the drive current by up to 107% due to higher compressive stress while the 3-stack NSFET can achieve an enhancement in drive current even up to 187% using a 30% Ge mole fraction. Furthermore, we compare the multiple stacked channel NSFETs and nanowire FETs (NWFETs) considering different strain techniques. As compared to a 3-stack strained-SiGe NWFET, NSFETs show 27% and 10% enhancements in ION and SS, respectively. Vertically stacked NSFETs are shown to be the best option to improve the hole mobility under biaxial and uniaxial compressive strain rather than NWFETs. We also look at how the Ge mole fraction affects various electrical properties in a uniaxial strained-SiGe channel with shrinking dimensions of scaled NSFETs. It is observed that for a fixed Lg, ION/IOFF ratio, SS and DIBL decrease with the increase in Ge mole fraction.

Compressive Strained Si1-XGex Channel for High Performance Gate-All-Around Nanosheet Transistors

As scaling of conventional FinFET architecture to achieve target transistor density and performance becomes more complex and difficult, it is essential to attain a next generation transistor architecture. Horizontal Gate-All-Around (hGAA) nanosheet (NS) devices have attracted attention as a candidate to replace FinFETs at the 5nm technology node and beyond due to their excellent electrostatics and short channel control. Compared to scaled FinFET, stacked GAA NS offers circuit performance improvements with increased effective width per active footprint while also enabling gate length scaling. Exploring performance improvement techniques, such as channel strain engineering, is important for next generation CMOS technologies. It is difficult, however, to effectively induce strain into the channel region using source/drain stressors in scaled GAA NS structures due to reduction of the stressor (embedded SiGe in source/drain region) volume as transistor dimension shrinks. In addition, strain relaxation of source/drain stressors caused by introduction of crystalline defects decreases effectiveness to induce strain into the channel region. This is more pronounced by the fact that achieving superior epitaxial growth is more difficult on the GAA NS device structure due to the presence of inner spacer dielectric. Therefore, we proposed a stacked GAA NS pFET device with compressively strained SiGe channel. The SiGe channel NS devices were fabricated using Si NS channel trimming by selective isotropic dry etch and selective SiGe epitaxial growth techniques after the Si NS channel release (Fig. 1). This is the preferable scheme in terms of strain retention in the SiGe channel NS region since there are no patterning processes that cause strain relaxation during downstream processing.To investigate the device characteristics of SiGe NS devices, we fabricated strained Si1-xGex (x = 0.2, 0.25, 0.3, and 0.35) channel NS pFET and investigated the crystallinity and strain in the channel region. Fig. 2 contains cross-sectional TEM images across the gate after Si0.7Ge0.3 channel formation. We observed no visible crystalline defects in the 4 nm-thick Si0.7Ge0.3 layer grown on the 2 nm-thick trimmed Si NS, indicating superior crystallinity of Si0.7Ge0.3 layer. To investigate strain in the nanoscale strained SiGe NS channel structures, Precession Electron Diffraction (PED) characterization was performed to evaluate lattice deformation of the stacked SiGe NS channel with 4 nm-thick Si0.7Ge0.3 epitaxial growth. Lattice deformation values are defined as the difference between in-plane lattice constants and the Si lattice constant, normalized by the Si lattice constant. Fig. 3 shows in-plane lattice deformation contour maps in the region of the stacked SiGe NS channel obtained from both X-cut (across the gate) and Y-cut (along the gate) for the SiGe NS structure with sheet width of 20 nm. The in-plane lattice deformation values were extracted from the middle of the SiGe NS channel as shown in Fig. 4. Preservation of half the amount of strain along the channel direction ([110]) was confirmed whereas strain along the NS width direction ([1-10]) was found to be almost fully relaxed due to elastic relaxation. This results in the Si0.7Ge0.3 channel being uniaxially stressed. The compressive stress along the channel direction estimated from the [110] lattice deformation is ~1 GPa.Normalized hole mobility in the representative Si1-xGex channel NS pFET as a function of inversion carrier density (Ninv) is shown in Fig. 5. The hole mobility of Si1-xGex channel (x = 0.35) with Si cap is almost 100% higher than that of Si NS channel. The mobility benefit of Si1-xGex channel is attributed to reduced effective hole mass along the transport direction caused by a high compressive strain in the Si1-xGex channel.The technique demonstrated in this study for forming compressively strained SiGe channel NS has great potential to improve pFET device performance for next generation of CMOS logic in GAA Nanosheet technology. Figure 1

Formation and Evaluation of Al2O3 Layer By Direct ALD on Epitaxial SiGe

In recent years, SiGe and Ge have drawn considerable attention as a high mobility channel material toward next-generation complementary metal-oxide-semiconductor (CMOS) circuits. In particular, by inducing strain into Ge using Ge/SiGe hetero-structure, highly enhanced mobility which greatly exceed the bulk mobility have been reported [1]. In order to obtain high mobility, it is necessary to generate larger strain. As one of the methods, strained SiGe on Ge-on-Si is expected. In addition, in order to realize a high mobility SiGe channel MOSFET, it is necessary to form the high-quality gate stacks and interfaces between a gate insulator film and a SiGe surface. In fact, the use of atomic layer deposition (ALD) or plasma oxidation has provided a high quality interface between Ge and the insulator film [2, 3]. However, unlike Si, wet cleaning of Ge or hydrofluoric acid treatment does not provide a high-quality hydrogen-terminated surface, and there is concern about surface oxidation and impurity adsorption. Therefore, we have attempted direct ALD on epitaxially grown Ge and reported that the Ge/Al2O3 interface properties are improved [4]. In the case of SiGe, a high-quality hydrogen-terminated surface cannot be obtained by wet cleaning or hydrofluoric acid treatment. For this reason, oxidation or impurity adsorption on the SiGe surface is feared. In this study, for the application to strained SiGe channel MOSFET, an Al2O3 film was formed using ALD on epitaxially grown SiGe as a gate stack structure on SiGe, and the interface structure was evaluated.Two types of samples were prepared by two methods. An n-type Ge (100) substrate was used in this study. The Ge substrate was chemically cleaned with NH4OH solution and followed by a HF dip and de-ionized water rinse. The wet-cleaned Ge substrate was loaded into an MBE chamber and subjected to thermal cleaning at 600 °C for 10 min. Subsequently, a 50 nm thick SiGe layer (called epi-SiGe hereafter) was hetero-epitaxially grown on the Ge substrate at 300 °C. The as-grown sample was subsequently transferred to the vacuum-connected ALD chamber and an Al2O3 film was deposited by ALD (Sample (A)). For comparison, after the epitaxial growth of the SiGe, the sample was once taken out from the chamber and exposed to the atmosphere for 5 min. The sample was then reloaded into the ALD chamber and an Al2O3 film was deposited (sample (B)). ALD of Al2O3 films was carried out for 20 cycles with precursors of TMA and H2O at a substrate temperature of 300 °C. Chemical bonding states were examined by x-ray photoelectron spectroscopy (XPS) using an ESCA-300 manufactured by Scienta Instruments AB.According to figs.1 (a) and (b), it was confirmed that the GeOx peak of the sample (A) transferred in a vacuum was significantly smaller than that of the sample (B) once exposed to the atmosphere. In particular, almost no Ge4+ peak [5] arising from Ge in GeO2 was observed, indicating that oxidation of Ge was suppressed by transport in vacuum. It is considered that the GeOx peak in the sample (A) is derived from the interface between Al2O3 and SiGe. According to figs.1 (c) and (d), no Si4+ component (binding energy range 102eV to 104eV) is found in the Si 2p 3/2 spectrum of the sample (A) transferred in a vacuum. In summary, XPS analyses reveal that formation of GeO2 and SiO2 by natural oxidation can be almost avoided by ALD on the epitaxial SiGe, and it is indicated that the Al2O3/SiGe interface created does not contain the interfacial GeO2 layer which is present for the sample exposed to the air before ALD. These results clearly indicate that the direct ALD on epitaxial SiGe is very promising way to highly improve the SiGe MOSFET performances.AcknowledgmentsThis work was partly supported by the MEXT Supported Program for the Strategic Research Foundation at Private Universities 2015–2019, a Grant-in-Aid for Scientific Research from MEXT and Interdisciplinary Research Center for Nano Science and Technology in Tokyo City University.

Strain compensation by relieving defects in SiGe channel for FinFET technologies

Current generations of FinFET devices are incorporating SiGe alloys as stressor material in channel regions in order to enhance hole mobility, drive current and channel conductivity. However, the presence of SiGe gives rise to new issues to be controlled during the device fabrication process, such as the strain retention or defectivity control, as they may seriously impact the quality of the strained SiGe channel and so the final device performance. The present work addresses the study of defect formation during the optimized integration of SiGe FinFETs for 10 nm technology nodes, aimed at determining the Ge threshold content for the nucleation of defects. Due to the relevance of atomistic models in determining the mechanisms and nature of defect formation, molecular dynamics (MD) simulations have been performed to emulate the FinFET fabrication process. The channel region is generated by removing a portion of the total volume of the Si substrate, further refilled with Si1 − xGex alloy to form the co-integrated FinFETs. After deposition, the presence of Ge induces a lattice distortion which is expected to be relieved by defect formation. Samples are annealed varying the Ge fraction, allowing to determine that threshold Ge content for the nucleation of defects is x = 0.27. MD provides also the nature of the formed defects, which have been suggested to be twinning developed at {111} planes and 60 ° misfit dislocations. Simulation results have been compared to experimental observations, both in good agreement.

Strain-engineering in nanowire field-effect transistors at 3 nm technology node

Abstract Toward extreme scaling of CMOS transistors, it is being predicted by IRDS that some sort of gate-all-around FinFET structure (nanowire or nanosheet type of devices) will be essential in 5 nm technology node and below. Thus, it is time for exploring new device structures through simulations. In this work, as a proof-of-concept, a comparative study of bulk-Si channel, Si-channel with epi-SiGe source/drain stressor and uniaxially strained-SiGe channel nanowire field-effect transistors at 3 nm technology node has been performed using predictive TCAD simulations. Uniaxial compressive strain due to lattice mismatch is found to be more effective for boosting device performance of strained-SiGe channel nanowire FETs. Detailed analyses of performance comparison with conventional bulk-Si channel nanowire transistors are reported.

Performance comparison of strained-SiGe and bulk-Si channel FinFETs at 7 nm technology node

Applications of stress/strain are now part of technology ‘boosters’ in microelectronics industry among other technologies such as silicon-on-insulator or the metal gate/high-k techniques. Application of strain in channel significantly increases carrier mobility. Thus, there is a need to characterize the deformations at nanoscale in the semiconductor induced by the strain. Uniaxial compressive strain has been an indispensable performance booster for p-channel FinFETs. In this work, based on extensive 3D process and device simulations with mechanical stress simulations using finite element techniques, performance assessment of nanoscale tri-gate FinFETs with uniaxially strained-SiGe channel (fin) has been presented. A comprehensive study based on stress tuning parameters is carried out to investigate the possible highest amount of process induced stress transfer to SiGe fin for optimization of device performance. The impact of process-induced strain on carrier mobility enhancement in 7 nm technology node is another major focus of this study. The stress transfer efficiency is shown for different process conditions with different Ge content. Technology CAD simulations show that strain in the fin is larger for higher Ge contents in the SiGe layer for p-channel FinFETs. For the first time, conversion from biaxial compressive strain of SiGe to uniaxial compressive strain in SiGe layers via process simulation has been demonstrated and implemented in the virtual fabrication of uniaxially strained-SiGe channel (fin) tri-gate FinFETs. A detailed performance comparison has been performed with conventional bulk-Si tri-gate FinFETs.

Electro-thermal assessment of heterojunction tunnel-FET for low-power digital circuits

To overcome the fundamental limitations of conventional MOSFETs, tunnel field effect transistors (TFETs) with strained-SiGe channel (via heterogeneous integration) may be used and is demonstrated using TCAD simulations. We mainly focus on the design and implementation of silicon-germanium (SiGe)-based tunnel field effect transistor, aiming to reduce the device operation voltage down to below 0.5 V. Physics-based electro-thermal simulations are performed for evaluating the self-heating (temperature rise) in the devices. We present the results of the electro-thermal analysis supported by effective 2D and 3D device simulations. Performance improvement in drain current as high as 200% has been achieved.

Electro-thermal assessment of heterojunction tunnel-FET for low-power digital circuits

To overcome the fundamental limitations of conventional MOSFETs, tunnel field effect transistors (TFETs) with strained-SiGe channel (via heterogeneous integration) may be used and is demonstrated using TCAD simulations. We mainly focus on the design and implementation of silicon-germanium (SiGe)-based tunnel field effect transistor, aiming to reduce the device operation voltage down to below 0.5 V. Physics-based electro-thermal simulations are performed for evaluating the self-heating (temperature rise) in the devices. We present the results of the electro-thermal analysis supported by effective 2D and 3D device simulations. Performance improvement in drain current as high as 200% has been achieved.

(Invited) Advanced Replacement High-K/Metal Gate Stack Engineering for High-Performance Strained Silicon-Germanium FinFETs with High Ge Content

Strained SiGe channel is attractive to further boost the performance of p-MOS FinFET due to its enhanced intrinsic transport properties and improved reliability compared to Si FinFET. With higher Ge incorporated in the channel, higher mobilities can be achieved, mainly due to the increased level of compressive strain. However, a major challenge is associated with the gate stack and interface trap control as the Ge content is increased. In this paper, key process details to enable relatively tall fins and optimized replacement high-k metal gate (RMG) stacks in high-Ge-content SiGe are discussed and their impact on key device characteristics are presented. In addition, our recent advancements to achieve optimized RMG interface layer and passivation to enable high performance short channel pMOS FinFETs are reviewed.

(Invited) Variability and Performance on FDSOI Technology with Strained SSOI Substrate and SiGe Channel

Fully Depleted SOI (FDSOI) technology has been introduced at the 28nm node as a low-cost alternative strategy to FinFET. Developments on-going on 22nm and 14nm demonstrates the interest of this technology for CMOS scaling. In this talk, mismatch on FDSOI technology will be presented in order to list the main contributors of local variability. Back-bias impact on electrical parameters and variability will be discussed. Then, the effect of strain boosters on device variability and performance will be presented, including strained SOI substrates (sSOI), SiGe channel and compressive/tensile CESL layer.

(Invited) UTBB FDSOI PMOSFETs Including Strained SiGe Channels at the 14nm Technology Node and Beyond

The 28 nm Ultra-Thin Body and Buried Oxide (UTBB) Fully Depleted Silicon-On-Insulator (FDSOI) technology is in production [4]. This technology addresses both high performance and low power / low voltage applications. Indeed, a 28 nm FDSOI Processor (CPU) has been demonstrated to run at 3 GHz for a 1.3 V supply voltage (Vdd), 1 GHz for 0.6 V, still 300 MHz at 0.5 V [1]. This latter result evidences the high potential of FDSOI for Low Voltage operation, required for the next handheld, mobile or Internet-of-Things markets. The 14nm FDSOI technology extends this offer to even more performance (+50% frequency at a given dissipated power), with a 100mV supply voltage reduction [5]. For the 14nm FDSOI, we have integrated SiGe channel, which enables to achieve high biaxial compressive stress due to the lattice mismatch between Silicon and Germanium. The compressive stress enhance the hole mobility, and in turn pMOSFETs performance. In such an approach, one of the main challenges is to conserve the strain during the CMOS integration. Especially, it is well known that the patterning of SiGe leads to partial relaxation close to the active edges. This relaxation affects especially the level of stress in the channel when the dimensions of the active are small. The stress configuration becomes thus strongly layout-dependent. We have physically and electrically characterized the strain-induced layout effects in SiGe pMOSFETs built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). This layout effect is reproduced by an accurate physics-based electrical model, which enable us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading to +21% effective current increase in short transistor at Lg=20nm gate length and in turn -15% delay reduction for ring-oscillator of 1-gate finger inverters. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Especially, a continuous-RX design, which consists in a long active line configuration, optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage [10]. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. For next UTBB-FDSOI nodes below 14nm, both the electrostatics and the carrier mobility must be improved. For the hole mobility, one may think about changing the crystalline orientation of the channel and using (110)-oriented substrates. However, in terms of electronic transport, the long channel carrier mobility is no longer the most relevant electrical parameter. One should pay a great attention to i) the strain compatibility and ii) the evolution of the apparent mobility with the gate length and width. Taking them into account, for pMOSFETs, SiGe channel + SiGeB source/drain + compressive contact etch stop layers in the (100) <110> direction is the best combination. For nMOSFETs, different technological solutions have been assessed, especially based on strain memorization techniques [6-7]. Strain-SOI substrates (sSOI) is another option, which brings enough performance boost to ensure a one-node scaling (+20-30% performance increase for nMOSFETs due to tensile strain, even for narrow active regions) [8]. Finally, the gate-last integration on planar FDSOI could be another strain booster because it leverages not only a low thermal budget for EOT and a threshold voltage optimization, but also a strain improvement during the final gate formation [9].

(Invited) UTBB FDSOI PMOSFETs Including Strained SiGe Channels at the 14nm Technology Node and Beyond

We have physically and electrically characterized pMOSFETs of compressively strained SiGe channel built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). Such a channel greatly contributes to the FDSOI CMOS high-performance at the 14nm node. At the same time, it induces strong layout effects, which are reported and explained in this paper. They can be reproduced by an accurate physics-based electrical model, which enables us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading experimentally to a -15 percent delay reduction for a ring-oscillator of 1-gate finger inverters at 0.8V supply voltage. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Namely, a continuous-RX design, which consists in a long active line configuration, optimizes the stress configuration, maintaining a high level of longitudinal compressive stress, while relaxing the transverse one. A 28 percent ring oscillator delay improvement is experimentally demonstrated at a given leakage for 1-finger inverter at 0.8V supply voltage. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. Finally, we discuss the technological knobs and especially the strain boosters that can furthers the scaling of FDSOI below the 14nm node: SiGe channel and source/drain of high-Ge content, influence of the surface orientation and channel direction, as well as the gate last integration.

(Invited) Variability and Performance on FDSOI Technology with Strained SSOI Substrate and SiGe Channel

Fully Depleted SOI (FDSOI) technology has been introduced at the 28nm node as a low-cost alternative strategy to FinFET. Developments on-going on 22nm and 14nm demonstrates the interest of this technology for CMOS scaling. In this talk, mismatch on FDSOI technology will be presented in order to list the main contributors of local variability. Back-bias impact on electrical parameters and variability will be discussed. Then, the effect of strain boosters on device variability and performance will be presented, including strained SOI substrates (sSOI), SiGe S/D and compressive/tensile CESL layer.

(Invited) 14nm FDSOI Technology for High-Speed and Energy-Efficient CMOS

As CMOS technology scales down, two paths are pursued by the industry to overcome the fundamental limits of traditional planar bulk transistors. One is the introduction of a Tri-Gate or FinFET transistor at the 22 and 16 nm nodes [1, 2]. These architectures provide impressive drive currents per footprint at low supply voltages because of the 3-D conduction channel and excellent electrostatic control. Conversely, they have high gate and parasitic capacitances, proportional to the 3-D effective W increase, which negatively impacts both the speed and active power consumption. Alternatively FDSOI provides an evolutionary path. First introduced at the 28nm node [3], FDSOI includes excellent mismatch properties, a simplified planar manufacturing process vs 3-D finFET technology and capitalization of existing design techniques. It also extends the possibility of back biasing and therefore offers unique “smart” solutions for dynamic power optimization [4]. The technology presented in this paper furthers the appeal of FDSOI to the 14nm node [5]. Compared to the 28nm technology, new Front-End process elements include a dual SOI/SiGeOI N/P channel, a dual workfunction gate-first HKMG integration scheme and a dual in-situ doped Si:CP/SiGeB N/P raised source-drain [5]. Additionally hybrid bulk areas, formed before Shallow Trench Isolation (STI), provide a space for passive devices and ESD FETs to be built [6]. The strained-SiGe channel (cSiGe) is realized before STI patterning to avoid SiGeOI over-thinning linked to the Ge condensation process at active edges [7] (Fig.1). As shown in Fig.1, strain into the channel has been experimentally measured by Nano-Beam Electron Diffraction (NBED) : 1% compressive strain in the 6nm thin SiGeOI channel (25%Ge) is demonstrated. After gate patterning, a N/P dual spacer/dual epitaxy scheme is used, as illustrated in Fig.2.Since gate-to-drain capacitance (Cgd) is of high importance for the circuit speed and power, spacer, poly thickness and raised source-drain epitaxy (Fig.2) has been optimised to minimize Cgd down to ~0.3fF/µm for both n and pMOS devices. cSiGe and SiGeB source-drain implementation in 14nm FDSOI provides a large pMOS drive current enhancement when compared to FDSOI technology at the 28nm node. As a result of low Cgd and large pMOS drive current, 14FDSOI technology demonstrated in [5] a -20% delay gain with the Fan-Out 3 (FO3) RO inverters at the same static leakage and a 100mV Vdd reduction (0.8V vs 0.9V) over the 28nm FDSOI technology (Fig.3). From this previous work, the transistor performance has further progressed and the delay boost is now established at -34% with -100mV Vdd operation, as shown in Fig.3. It means >50% speed frequency in 14FDSOI at 0.8V Vdd vs 28FDSOI at 0.9V Vdd. These large performance enhancements over 28FDSOI make 14FDSOI as a leading edge technology for the 14nm node and a highly competitive technology for low voltage and energy efficient CMOS applications.

(Invited) Strained-SiGe Channel FinFETs for High-Performance CMOS: Opportunities and Challenges

The effectiveness of widely-used CMOS stressors, such as compressive stress liners and embedded source/drain is significantly decreased in the state-of-the-art CMOS as the gate pitch is scaled down and device architecture is transformed from planar to 3D non-planar architectures, such as FinFETs. The issue is more pronounced for FinFETs fabricated on the SOI substrates. It is well known that SiGe is a great candidate for p-type MOSFETs due to its intrinsic lower effective mass and better transport properties than Si and has been utilized in CMOS industry for IBM SOI 32nm and 22nm generations, as a key knob to adjust the PFET threshold voltage and performance enhancement [1, 2]. However, it is shown that SiGe with moderate Ge content and no strain does not provide noticeable transport (neither long-channel nor short-channel) benefit over Si and it is believed that the strain plays a significant role in high-performance (HP) SiGe channel pFETs [3]. The strain state in typical thin SiGe substrates grown on bulk Si or SOI is biaxial compression. It has been shown that by patterning of biaxially strained SiGe layers, strain can be transformed to asymmetric strain (uniaxial for FinFET) where the effective mass is significantly lowered and higher hole velocities can be achieved. Hole transport can be significantly improved by increasing the Ge content as well as the built-in strain, while the second component (strain) has a stronger impact on the transport enhancement. However, higher-Ge content SiGe offers reduced bandgap and may result in increased gate-induced –drain-leakage (GIDL) and high off current due to increased band-to-band or trap-assisted tunneling. This brings concern for some CMOS applications, such as I/O devices and SRAM. Moreover, the interface passivation for higher Ge content SiGe is extremely challenging and can cause significant sub-threshold leakage and degraded low field mobility. The direct consequence is the degraded short-channel on-state current at the target off-current at a scaled power-supply voltage, VDD. In order to experimentally investigate the device characteristics of SiGe FinFETs, we have fabricated strained-Si1-xGex-on-insulator pMOS FinFETs with Ge fraction, x~0.3-0.5 using CMOS-compatible process flows which allow us co-integration with Si or strained-Si for n-type transistors. Highly-compressively-strained SGOI substrates were fabricated using Ge condensation processes and strain transformation to uniaxial was verified by Raman spectroscopy. A gate-first high-K/metal-gate flow with ion-implant-free raised-S/D and aggressively scaled fin and spacer dimensions has been developed to fabricate devices with aggressively scaled gate lengths [4]. A Si-cap-free scheme was developed for the interface passivation to allow CET scaling and eliminate the epitaxial related issues on the 3D architectures. We have observed that non-optimized passivation may result in relatively high interface trap densities and sub-threshold slopes (SS) around 75-80mV/dec for x~0.3 and over 80mV/dec for x~0.5. However, by optimizing the passivation process using a Si-cap-free approach, impressive SS=65mV/dec and 68mV/dec has been achieved for SGOI FinFETs with x~0.3 and x~0.5, respectively. Moreover, significant transport benefit in terms of mobility and drive current has been achieved due to the improved passivation [5]. As a result, we have reported superior mobility characteristic for SGOI pMOS FinFETs with x~0.5 over the state of the art Si, SiGe or relaxed-Ge FinFETs [6]. We have also investigated the short-channel GIDL characteristics of surface-channel strained-Si1-xGex pMOS FinFETs. We have shown devices having a minimum GIDL current of 1nA/μm for x~0.3 and 20nA/μm for x~0.5 at an operating voltage of VDD=0.8V and an operating temperature of 50°C. Temperature-dependent leakage current measurements demonstrate that the GIDL caused by band-to-band tunneling is the dominant leakage mechanism as compared to trap-assisted tunneling for both cases [7]. In summary, we have reported process integration and electrical characterization of SGOI FinFETs with aggressively scaled gate and fin dimensions and Ge content x~0.3-0.5 using an improved Si-cap-free surface passivation process. SiGe-OI FinFETs with x~0.3 can offer superior pMOS characteristics and are promising candidate for both high-performance and low-power applications. On the other hand, while SiGe-OI FinFETs with x~0.5 can offer extremely high mobility and high current drive and transconductance which is applicable to high-performance CMOS, their operation even at low VDD could be a concern for low-power applications, similar to the state-of-the-art Ge FinFETs [8]. S. Krishnan et al., IEEE IEDM, 634 (2011).C. Ortolland et al., IEEE IEDM, 236 (2013).A. Khakifirooz et al., IEEE EDL, 34, 1358 (2013).P. Hashemi et al., Symp. VLSI Tech., 18 (2013).P. Hashemi et al., Symp. VLSI Tech., 18 (2014).P. Hashemi et al., IEEE IEDM, 16.1 (2014).K. Balakrishnan et al., IEEE DRC, 183 (2014).B. Duriez et al., IEEE IEDM, 522 (2013).

(Invited) Strained-SiGe Channel FinFETs for High-Performance CMOS: Opportunities and Challenges

Strained Silicon-Germanium (s-Si1-xGex) FinFET is a promising pMOS candidate for sub-10nm technology generations due to its superior hole transport properties over Si FinFETs, which is a result of built-in uniaxial compression. In this paper, we discuss process integration challenges and opportunities as well as electrical characterization of s-Si1-xGex–on-Insulator (SiGeOI or SGOI) FinFETs with aggressively scaled gate and fin dimensions and Ge content up to x~0.5, using an improved Si-cap-free surface passivation process. The device electrostatics, hole transport, impact of surface passivation, and drain leakage characteristics of SiGeOI pMOS FinFETs are comprehensively studied. The results indicate that SiGeOI FinFETs with moderate Ge content of x~0.3 can offer superior pMOS characteristics and are promising candidate for high-performance (HP) and some low-power applications (LP). On the other hand, while SiGeOI FinFETs with higher Ge content (x~0.5) can offer extremely high mobility and high current drive which is applicable to high-performance CMOS, their off-state leakage could be a concern for low-power applications.

Mobility Enhancement and Gate-Induced-Drain-Leakage Analysis of Strained-SiGe Channel p-MOSFETs with Higher-κ LaLuO3 Gate Dielectric

A strained-SiGe p-channel metal-oxide-semiconductor-field-effect transistors (p-MOSFETS) with higher-κ LaLuO3 gate dielectric was fabricated and electrically characterized. The novel higher-κ (κ∼30) gate dielectric, LaLuO3, was deposited by molecular-beam deposition and shows good quality for integration into the transistor. The transistor features good output and transfer characteristics. The hole mobility was extracted by the splitting C—V method and a value of 200cm2/V·s was obtained for strong inversion conditions, which indicates that the hole mobility is well enhanced by SiGe channel and that the LaLuO3 layer does not induce additional significant carrier scattering. Gate induced drain leakage is measured and analyzed by using an analytical model. Band-to-band tunneling efficiencies under high and low fields are found to be different, and the tunneling mechanism is discussed.