Static Timing Analysis Research Articles

Revisiting Union: A New Perspective on an Old Outcome.

Background:To present the inherent and unique challenges associated with utilizing fracture healing as an outcome measure in foot and ankle orthopedics, specifically the statistical methods used in assessing time to union.Methods:In a previously published manuscript assessing the effect of delayed weightbearing on time to union following intramedullary (IM) screw fixation of Jones (Zone 2 fifth metatarsal base) fractures, patients were divided into early weightbearing (EWB, n=20) and delayed weightbearing (DWB, n=21) cohorts (within or beyond 2 weeks, respectively). Time to union was determined and compared between the 2 cohorts using cumulative link model analysis, with delayed union (12.5 weeks) defined from established literature.Results:Cumulative link model analysis demonstrated no significant differences in time to union (EWB: 25% by 6th week, 55% by 12th week; DWB: 33% by 6th week, 43% by 12th week; P = .819) or delayed unions (EWB, 20% vs DWB, 24%; P > .999).Conclusion:Our analysis using cumulative link models, or ordinal regression, in the statistical analysis of time to union, determined that that early weightbearing following IM screw fixation in Jones fractures appeared to be safe without delaying fracture healing. This statistical approach can be considered when describing a continuous outcome captured by infrequent observations.

Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow

A self-timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing-driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low-power self-timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing-driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing-driven synthesis and static timing analysis. Finally, two 32-bit RISC-V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock-gating and SynV without clock-gating.

Design and tool flow of a reconfigurable asynchronous neural network accelerator

Convolutional Neural Networks (CNNs) are widely used in computer vision, natural language processing, and so on, which generally require low power and high efficiency in real applications. Thus, energy efficiency has become a critical indicator of CNN accelerators. Considering that asynchronous circuits have the advantages of low power consumption, high speed, and no clock distribution problems, we design and implement an energy-efficient asynchronous CNN accelerator with a 65 nm Complementary Metal Oxide Semiconductor (CMOS) process. Given the absence of a commercial design tool flow for asynchronous circuits, we develop a novel design flow to implement Click-based asynchronous bundled data circuits efficiently to mask layout with conventional Electronic Design Automation (EDA) tools. We also introduce an adaptive delay matching method and perform accurate static timing analysis for the circuits to ensure correct timing. The accelerator for handwriting recognition network (LeNet-5 model) is implemented. Silicon test results show that the asynchronous accelerator has 30% less power in computing array than the synchronous one and that the energy efficiency of the asynchronous accelerator achieves 1.538 TOPS/W, which is 12% higher than that of the synchronous chip.

SPUF design based on Camellia encryption algorithm

To meet the security requirements of resource-constrained systems, a software PUF (SPUF) scheme based on the encryption algorithm is proposed using the timing violation to generate the chip’s fingerprint. In this work, the Camellia encryption algorithm is selected and implemented via a semi-custom design flow to get the deviation of circuit delay. And then, the delay time of critical path of the proposed circuit is generated through static timing analysis. Using the overclocking frequency, the Camellia encryption algorithm circuit operates at timing violation status. We can collect the wrong response data of the simulation result at different input signals. The wrong data caused by timing violation can be defined as output of SPUF, which is the chip’s fingerprint. To improve the randomness, the multi-round operation of the Camellia is used to process the SPUF data. The experimental results show that the uniqueness of SPUF is 50.01%, the SPUF data passes the NIST test, and no additional hardware overhead is required.

Machine Learning for On-the-Fly Reliability-Aware Cell Library Characterization

Aging-induced degradation imposes a major challenge to the designer when estimating timing guardbands. This problem increases as traditional worst-case corners bring over-pessimism to designers, exacerbating competitive and close-to-the-edge designs. In this work, we present an accurate machine learning approach for aging-aware cell library characterization, enabling the designer to evaluate their circuit under the impact of precisely selected degradation. Unlike state of the art, we bring cell library characterization to the designer, empowering their capability in exploring the impact of aging while protecting confidential information from the foundry at the same time. Furthermore, the fast inference of cell libraries makes it feasible, for the first time, to examine aging-induced variability analysis in a Monte-Carlo fashion. Finally, we show that the designer is able to select a less pessimistic timing guardband by choosing adequate delta threshold voltage ( ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) for their design and their needs. Our machine learning approach reaches an R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> score of $>99\%$ for almost all data stored in the cell library. Only timing constraints show slightly less accuracy with an R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> score around 95%. When using ML-characterized libraries in static timing analysis, we achieve errors smaller than ±0.5% and ±0.1% for path delay and dynamic power, respectively. Errors in leakage power are negligible and even smaller by orders of magnitude. Our machine learning implementation for standard cell library characterization is publicly available. Download: https://opensource.mlcad.org

OpenTimer v2: A Parallel Incremental Timing Analysis Engine

Editor's note: This article introduces a high-quality open-source static timing analysis engine that is capable of parallel incremental timing and that provides an efficient API to facilitate development of complex EDA tools. - Sherief Reda, Brown University - Leon Stock, IBM - Pierre-Emmanuel Gaillardon, University of Utah

Causal Path Identification for Timed and Sequential Circuits

Self-timed and pulse mode circuit modules are often implemented using combinational logic with feedback, or require timing constraints for the circuit to function correctly. Identifying causal paths through these circuit modules is a fundamental requirement to enable automatic system level timing closure, performance analysis, and timing-driven optimizations when using static timing analysis algorithms. A methodology and algorithm for identifying causal paths in cyclic sequential circuits under arbitrary timing models are presented. The algorithm identifies causal paths in a sequential circuit implemented with standard cell gates. The algorithm is demonstrated by identifying causal paths for over 100 asynchronous finite-state machines and timed circuits designed using a variety of timing models. Cyclic paths, pulse generating paths, and unbounded length self-enabling loops are identified inside these circuit blocks. Some of the causal paths in these designs have never been previously identified. No preliminary versions of this work have been previously published.

Characterization and hierarchical static timing analysis of mixed-signal design

As the technology grows, the tendency to increase the data rate also increases. Clocks with higher frequencies have to be generated to meet the increased data rate. Any mismatch between the clock rate and data rate will lead to the capture of the wrong data. Hence performing timing analysis for any design to validate the capture of correct data plays a major role in any System on chip. This paper explains the procedure followed to perform timing analysis for any mixed-signal design.

Design of 64-Bit Arithmetic Logic Unit Using Improved Timing Characterization Methodology for RSFQ Cell Library

Accurate timing characterization of library cells is essential for adopting the standard digital design flow using EDA tools, such as static timing analysis (STA) with timing back-annotation. For RSFQ circuits, the propagation delay of a cell is influenced by the input and output load. We have developed an automated timing characterization methodology that facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. While being highly accurate, such a comprehensive timing characterization requires a large number of simulation runs. To significantly reduce the total number of simulation runs, we propose to analyze independently, rather than jointly, the effect of succeeding cells with standard preceding load and preceding cells with standard succeeding load. In addition, for succeeding cells with a storage loop, the delay of a cell is dependent on the state of the succeeding cell. STA tools cannot account for state-dependent timing variations. To mitigate state-dependent timing constraint violations, a state-dependent timing correction is added to the hold/set-up time. We have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. We have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the three timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks.

ACR BI-RADS Category 3 Lesions in Women Younger Than 30: Follow-up Outcomes and Factors Associated With Biopsy.

Investigate imaging follow-up patterns and assessment of malignancy rate of BI-RADS 3 lesions in women younger than 30 years. We retrospectively reviewed consecutive studies between January 1, 2013 and January 1, 2015 with BI-RADS 3 assessment in women <30 years. Lesion size, follow-up rate, and biopsy rate were recorded. Completion of 24-month imaging follow-up or biopsy determined the endpoint. Statistical analysis of follow-up rates and biopsy timing was performed. Of 2525 BI-RADS 3 lesions, 278 were identified in 215 women <30 years. Fifty-two (24%) women underwent a biopsy which was more frequently done at patient request than for lesion growth [33 (63.4%) versus 19 (36.5%), P <.01]. The odds of having biopsy upfront was significantly higher in lesions >2 cm in diameter (OR: 4.4 [95% CI 2.1-9.4], P <.01). The malignancy rate in our cohort was 0% (95% CI 0-1.7%). Of the 188 women expected for follow-up imaging, 58 (30%) were lost to follow-up, while 103 (55%) had 6-month follow-up, 74 (39%) 12-month follow-up, and 56 (30%) 24-month follow-up. BI-RADS 3 lesions identified in our cohort had high biopsy rates and low compliance with no cancers. Our findings suggest that probable fibroadenomas in young women may only warrant abbreviated short-term follow-up at 6-months.

Сравнение открытых маршрутов проектирования цифровой аппаратуры: qFlow, OpenLANE, Coriolis, SymbiFlow

This paper reviews open-source tools for the logical synthesis, place-and-route, static timing analysis and topology generation hardware design stages. The following tools have been described: qFlow, OpenLANE, Coriolis, and SymbiFlow. These tools are aimed to synthesize RTL models into FPGA bitstreams or GDS II physical layouts. A PicoRV32 implementation of RISC-V microprocessor has been used for experimental evaluation of these flows. The results show that open-source flows are capable to produce physical layouts for realistic examples. At the same time, commercial CADs allow generating more effective designs in terms of clock frequency.

AVATAR: NN-Assisted Variation Aware Timing Analysis and Reporting for Hardware Trojan Detection

This paper presents AVATAR, a learning-assisted Trojan testing flow to detect hardware Trojans placed into fabricated ICs at an untrusted foundry, without needing a Golden IC. AVATAR is a side-channel delay-based testing solution that is assisted by a learning model (process watchdog) for tracking the process drift and systematic process variation. AVATAR’s process watchdog model is trained using a limited number of test samples, collected at test time, to tightly correlate the Static Timing Analysis results (generated at design time) to the test results (generated from clock frequency sweeping test). The experimental results confirm that AVATAR detects over 98% of (small) Trojans inserted in the selected benchmarks. We have complemented our proposed solution with a diagnostic test that 1) further reduces the false-positive rate of AVATAR Trojan detection to zero or near zero, and 2) pinpoints the net-location of the Trojan Trigger or Payload.

Cross-Corner Delay Variation Model for Standard Cell Libraries

For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of process, voltage, and temperature (PVT) conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating modes, each of which requires delay characterizations at nearby PVT corners. Furthermore, advanced technologies nodes suffer from corner explosion : while the impact of PVT variations is being exacerbated, process variations are also diversifying, increasing the number of operating conditions exponentially. This paper revisits the importance of cross-corner timing estimations and proposes a delay variation model to mitigate such corner explosion. Our objective is to reduce PVT corner characterization effort for timely static timing analysis on an exploding number of operating conditions. Our proposed Decomposed Propagation Vector Variation Model (DPVVM) decomposes propagation delay and timing constraints into the driving by the receiver cell and its driver cell; by scaling them separately, delay characterization effort is reduced to a fraction of time while realizing accurate timing estimations. We also propose Multi-Dimension Recomposition (MDR) scheme, which exploits a multitude of pre-characterized corners to further improve the consistency of cross-corner timing estimations. As a result, with only 8.0% of a corner characterization effort compared to the full-characterization, DPVVM combined with MDR achieves overall cross-corner timing estimation errors of 4.8% and 5.6% for single cells and complex logic circuits—or improvements of 69% and 61% over the conventional derating method, respectively. Our proposed method’s characterization overhead is 11% over the conventional derating method; the overhead is marginal, accounting for only 0.76% of a full-characterization time.

A Multitask-Aided Transfer Learning-Based Diagnostic Framework for Bearings under Inconsistent Working Conditions.

Rolling element bearings are a vital part of rotating machines and their sudden failure can result in huge economic losses as well as physical causalities. Popular bearing fault diagnosis techniques include statistical feature analysis of time, frequency, or time-frequency domain data. These engineered features are susceptible to variations under inconsistent machine operation due to the non-stationary, non-linear, and complex nature of the recorded vibration signals. To address these issues, numerous deep learning-based frameworks have been proposed in the literature. However, the logical reasoning behind crack severities and the longer training times needed to identify multiple health characteristics at the same time still pose challenges. Therefore, in this work, a diagnosis framework is proposed that uses higher-order spectral analysis and multitask learning (MTL), while also incorporating transfer learning (TL). The idea is to first preprocess the vibration signals recorded from a bearing to look for distinct patterns for a given fault type under inconsistent working conditions, e.g., variable motor speeds and loads, multiple crack severities, compound faults, and ample noise. Later, these bispectra are provided as an input to the proposed MTL-based convolutional neural network (CNN) to identify the speed and the health conditions, simultaneously. Finally, the TL-based approach is adopted to identify bearing faults in the presence of multiple crack severities. The proposed diagnostic framework is evaluated on several datasets and the experimental results are compared with several state-of-the-art diagnostic techniques to validate the superiority of the proposed model under inconsistent working conditions.

Effects of different droplet dispersion modeling methods on diesel spray simulation in Eulerian-Lagrangian framework

The realistic prediction of spray dynamics and dispersion is one of the main tasks of the combustion simulations in diesel engines. Usually, droplet dispersion modeling accuracy can be improved by the development of turbulence models and stochastic dispersion models. Although droplet dispersion due to turbulence is an important phenomenon in high-velocity fuel sprays, studies on the effect of these models are relatively few. Among these studies, the influence of a common used stochastic dispersion model on spray dynamics is not well understood and the application of hybrid turbulence models to fuel spray simulation in the Eulerian-Lagrangian framework with two-way coupling is still at starting stage. In the present study, a better understanding of the effect of the stochastic model on spray dynamics can be obtained by using a statistical analysis of stochastic dispersion time and velocity of dispersed droplets. In order to assess the ability of the hybrid model to improve the radial spread and the inhomogenous distribution of small droplets produced by a high-pressure injector, a partially averaged Navier-Stokes (PANS) model is implemented in an open-source code OpenFOAM and is compared with an unsteady Reynolds averaged Navier-Stokes (RANS) model and a large eddy simulation (LES) model. The results show the importance of resolving large-scale turbulent structures on droplet dispersion modeling in high-velocity fuel spray simulation. The common stochastic dispersion model used in RANS developed for homogenous, isotropic turbulent flows leads to the non-physical dynamics and distribution of droplets and hence is not applicable to the droplet dispersion which is dominated by the non-stochastic motion of large-scale structures in free shear layers. Using PANS instead of RANS should improve the droplet dispersion modeling accuracy of high-velocity fuel sprays in the development of diesel engines with an advanced injection system.

Speeding Up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions

Functional timing analysis (FTA) is a renowned method of finding the true critical delay for the design under interest. By constructing conjunctive normal form (CNF) clauses based on temporal and function constraints, false paths can be identified through the satisfiability (SAT) solving. As a result, the critical delay estimated by FTA is more accurate than that by conventional static timing analysis (STA). However, FTA suffers from the extremely long formulation and computation time, as the number of the clauses in CNF grows exponentially with the increasing size of the design. Due to the reconvergent effect, thousands of clauses can be redundantly formulated for one pin. Even worse, most of them are found useless but seriously lengthen the computation time. Therefore, to avoid ineffective computation in FTA, three novel techniques are proposed: 1) encoding duplication removal (EDR) for removing duplicated functional literals; 2) redundant state propagation (RSP) for propagating temporal states to identify redundant clauses; and 3) temporal footprint identification (TFI) for combining clauses that represent constraints with the same behavior. The experiments show that under a given timing constraint, 94% clauses and 95% literals can be pruned averagely (99% clauses and 99% literals under the best case), resulting in $15.3 \times $ speedup ( $72.99 \times $ under the best case) for formulation and SAT solving. As a result, the proposed techniques (EDR, RSP, and TFI) are proven effective to reduce useless computation and improve the overall performance of FTA.

A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools

The “event-driven” feature of asynchronous circuits enables the circuits to work when and where needed, making it a good alternative to design low-power circuits. However, asynchronous circuits are not widely adopted as a consequence of the lack of support by conventional EDA tools. In this article, we propose a novel design flow to implement the Click-based asynchronous bundled-data circuits efficiently down to mask layout with conventional EDA tools. To ensure timing correctness, we put forward an adaptive delay matching (ADM) method and perform accurate static timing analysis for the circuits. Compared with other asynchronous toolsets, the proposed design flow is more efficient and convenient to implement asynchronous circuits. An asynchronous convolution neural network accelerator is implemented in TSMC 180- and 65-nm CMOS process, respectively, to verify the proposed design flow. The silicon test results show that the asynchronous accelerator <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</b> as 30% less power in the computing array than the synchronous one in the TSMC 65-nm CMOS process, and the energy efficiency of the asynchronous and synchronous accelerators are 1.539 TOPS/W and 1.37 TOPS/W, respectively. The energy efficiency of the asynchronous accelerator in the TSMC 180-nm CMOS process is 133 GOPS/W.

Performance analysis of FSO link under the effect of fog in Delhi region, India

Abstract Fog attenuation causes more loss than other weather conditions in a free space optics (FSO) link thus limiting the visibility distance. This work presents a detailed survey on the attenuation of the transmitted signal as a result of variation in visibility range caused by different fog conditions of the Delhi, Safdarjung region. Kim and Kruse models have been used to calculate attenuation as a result of fog conditions for three specific months (January, February and December) for seven consecutive years starting from 2013 to 2019. Received signal quality has been analyzed as a function of transmitted power, data rate, transmission range and operation wavelength. Descriptive statistical analysis of real time observed visibility data allows for the estimation of specific optical attenuation and enables in determining the link availability of the region for the complete year.

Performance analysis of FSO link under the effect of fog in Delhi region, India

Abstract Fog attenuation causes more loss than other weather conditions in a free space optics (FSO) link thus limiting the visibility distance. This work presents a detailed survey on the attenuation of the transmitted signal as a result of variation in visibility range caused by different fog conditions of the Delhi, Safdarjung region. Kim and Kruse models have been used to calculate attenuation as a result of fog conditions for three specific months (January, February and December) for seven consecutive years starting from 2013 to 2019. Received signal quality has been analyzed as a function of transmitted power, data rate, transmission range and operation wavelength. Descriptive statistical analysis of real time observed visibility data allows for the estimation of specific optical attenuation and enables in determining the link availability of the region for the complete year.

Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology

In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC) model is integrated and solved self-consistently within the BSIM-CMG model. This allows the creation of NC-FinFET standard cell libraries, while considering the effects of various variability sources both in the ferroelectric layer as well as in the underlying constituent FinFET device. The variability-aware NC-FinFET libraries, fully compatible with the existing standard design flow of circuits, are then employed to perform simulations using commercial statistical timing analysis tools in order to study the performance of a 14nm processor. For comprehensive analysis and comparisons, our implementation is done for both NC-FinFET and conventional (baseline) FinFET for a wide range of voltages. Our results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability. Results also reveal that neglecting process variations leads to overestimating the benefit that NC brings to the processor’s frequency improvement because of the larger timing guardband that is needed to overcome variability in NC-FinFET.