Abstract
The “event-driven” feature of asynchronous circuits enables the circuits to work when and where needed, making it a good alternative to design low-power circuits. However, asynchronous circuits are not widely adopted as a consequence of the lack of support by conventional EDA tools. In this article, we propose a novel design flow to implement the Click-based asynchronous bundled-data circuits efficiently down to mask layout with conventional EDA tools. To ensure timing correctness, we put forward an adaptive delay matching (ADM) method and perform accurate static timing analysis for the circuits. Compared with other asynchronous toolsets, the proposed design flow is more efficient and convenient to implement asynchronous circuits. An asynchronous convolution neural network accelerator is implemented in TSMC 180- and 65-nm CMOS process, respectively, to verify the proposed design flow. The silicon test results show that the asynchronous accelerator <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</b> as 30% less power in the computing array than the synchronous one in the TSMC 65-nm CMOS process, and the energy efficiency of the asynchronous and synchronous accelerators are 1.539 TOPS/W and 1.37 TOPS/W, respectively. The energy efficiency of the asynchronous accelerator in the TSMC 180-nm CMOS process is 133 GOPS/W.
Highlights
Asynchronous circuits have significant potential advantages in low power consumption and high performance [1][2]
Conventional EDA tools such as Synopsys Design Compiler (DC) and IC Compiler (ICC) are used in the design flows proposed in [7][8] to design asynchronous BD circuits, in which, timing paths are obtained by using command “get_timing_path” by specifying them one by one and delay matching is performed by using command “set_min_delay” in DC tools
We put forward a design flow to implement Click-based asynchronous BD circuits using conventional EDA tools efficiently down to mask layout in this paper
Summary
Asynchronous circuits have significant potential advantages in low power consumption and high performance [1][2]. In [9] [10], a combination of clocks is adopted to describe every possible event propagation path in the design based on the Signal Transition Graph (STG), allowing the EDA tools to fully capture the relative timing constraints. This method can be used to perform STA on asynchronous BD circuits in the whole design flow. We propose an efficient and convenient design flow to implement Click-based (that is, Click element is adopted as control circuits) asynchronous BD circuits with conventional EDA tools.
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