Statistical Static Timing Analysis Research Articles

Finding the longest delay paths for the array-form multipliers using a genetic algorithm

Traditional digital multipliers are often designed in array forms or other variants. Timing of array-form multipliers can be analyzed by static timing analysis (STA), but the obtained timing result is conservative and pessimistic. Although statistical static timing analysis (SSTA) can partly solve the pessimism, it still does not generate test patterns for those near-to-longest delay paths. Finding near-to-longest delay paths can be helpful to designing error tolerant circuits, with which aggressive timing (with timing violation) can be exploited. In such design scenarios one should find test vectors to activate those near-to-longest delay paths in order to further run SPICE-precision diagnose on those potential timing violating critical paths. Test vector generation for such a testing problem is essentially an exhaustive enumeration problem when dealing with different forms of array multipliers. However, large size multipliers would result in an extremely large enumeration space for finding the longest delay path (LDP) test vectors. Currently there is no deterministic method that can guarantee to find test vectors for exact LDPs of a large size multiplier. Only very few research papers have addressed this problem, proposals are limited to heuristic methods without guarantee of finding the LDPs with the testing vectors. This paper investigates the potential of a genetic algorithm (GA) for searching the extensive test pattern space. By a fine design of GA, experimental running shows that a combination of well tuned evolutionary operators does empower the possibility of finding the LDPs for a set of moderate size carry-save adders (CSA) multipliers with the wordlength (WL) up to 25 bits on a plain laptop computer. Statistical properties of the proposed GA are examined.

Statistical static timing analysis via modern optimization lens: I. Histogram-based approach

Statistical Static Timing Analysis (SSTA) is studied from the point of view of mathematical optimization. We present two formulations of the problem of finding the critical path delay distribution that were not known before: (i) a formulation of the SSTA problem using Binary–Integer Programming and (ii) a practical formulation using Geometric Programming. For simplicity, we use histogram approximation of the distributions. Scalability of the approaches is studied and possible generalizations are discussed.

Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process Variation

As CMOS devices become smaller, aging-induced and process variations become major issues for circuit reliability. In this paper, a statistical gate sizing method is proposed to improve the lifetime reliability of manufactured chips in the presence of process variations and aging effects. To this end, we propose a canonical first order delay model to estimate the delay degradation of a gate under negative bias temperature instability and process variations considering spatial correlations. Using the proposed gate delay model, a statistical static timing analysis method is introduced to compute the circuit delay considering the joint effect of process variation and negative bias temperature instability. To guarantee that the circuit meets the required timing constraints, we propose an incremental gate sizing technique. This technique first computes the criticality of each gate defined as the probability that a gate lies on the critical path due to negative bias temperature instability and process variations. Then, a group of gates with the highest ranking according to criticality is chosen for a gate sizing-based timing optimization. It is worth nothing that, by using the proposed statistical gate delay model, we can compute the criticality of each gate incrementally. Experimental results based on ISCAS’85 benchmark circuits show that the proposed method can improve the lifetime reliability defined as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1(\mu + 3\sigma)$ </tex-math></inline-formula> of the initial delay distribution of the circuit at the expense of 8.64% area overhead. In comparison with the path-based method, the proposed approach is much faster, especially for larger circuits, which makes it a viable solution to optimize the lifetime reliability of very large-scale circuits used in industry.

Timing analysis algorithm using a neural network under PVT variations

Process-voltage-temperature variations result in an increase in logic gate delays, which further lead to timing violations. Because of the computational complexity of the operators such as max and sum in statistical static timing analysis, this paper proposes a timing analysis algorithm using neural network to evaluate circuit timing under the PVT variations. In the proposed algorithm, a neural network method is applied to model the mean or standard deviation of the gate delay. Then, a viability analysis method is introduced to recognize the true critical path. The simulation results on ISCAS89 benchmarks illustrate that compared with SPICE Monte Carlo simulation, the error in the mean calculated by the proposed algorithm is less than 2%, and the error in the standard deviation is less than 3.64%. In addition, for s298, s344, s832, s1238 and s13207, the viability analysis algorithm achieves 1.04X, 1.01X, 2.77X, 1.62X and 4.48X speedup over full path search, respectively.

Exact Distribution of the Max/Min of Two Correlated Random Variables

Statistical static timing analysis involves the distributions of the maximum and minimum of correlated random variables. Nadarajah and Kotz (IEEE Trans Very Large Scale Integr Syst 16:210–2012, 2008) derived closed form expressions for the distributions when the random variables are Gaussian. Here, we extend the work when the random variables follow a wide range of non-Gaussian distributions.

QSSTA: A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single flux quantum (SFQ) technology is an ultra-high performance and low power technology. The technology, however, lacks many of the design automation tools and capabilities that are commonplace in CMOS technology. This article describes methods to efficiently find the conditional probability density function (PDF) of the minimum workable clock period of SFQ circuits in view of manufacturing-induced process variations and presents qSSTA, a statistical static timing analysis tool targeting SFQ circuits. Following a grid-based correlation model, qSSTA represents spatial correlation of SFQ gates at different positions with respect to process parameters. By approximating timing characteristics of SFQ gates in a linear model, qSSTA is able to estimate the clock period as a normal random variable. Furthermore, process variations that generally result in extra delays in CMOS circuits can result in functional errors in SFQ circuits. qSSTA derives the closed form of the conditional PDF of the clock period under the scenario where all SFQ gates in the circuit work correctly. Compared to Monte Carlo simulations on look-up tables, experimental results show that the average percentage errors are 0.89% for the mean values, 8.04% for the standard deviation, and 0.61% for the 98-percentile point, whereas the runtime of qSSTA is 83% faster on average.

Circuit Reliability Comparison Between Stochastic Computing and Binary Computing

Reliability-enhanced circuit design is increasingly demanded due to severer transistor aging and variations at nanoscale. In this brief, new insights of inherently enhancing reliability are presented, based on the emerging computing paradigm of stochastic computing (SC). A new cross-layer reliability simulation flow supporting statistical static timing analysis (SSTA) is proposed, with a new long-term compact transistor aging model validated by 16/14nm FinFET experimental data. Then, the reliability of SC circuits in practical applications is investigated and compared with that of conventional binary circuits, for the first time. The results indicate that, the performance of SC circuits is intrinsically resistant to aging and variations ascribed to the circuit topology and the probability encoding. It suggests that, SC can provide more relaxed circuit design margins, offering promises to the application of emerging nanodevices in the future.

NN-SSTA: A deep neural network approach for statistical static timing analysis

Discrete statistical static timing analysis (SSTA) performs the timing analysis by using statistical maximum and convolution operations. The maximum is basically a non-linear operator and it is not a simple task to capture the skewness introduced by it. On the other hand, the convolution has a potential to “blow-up” the number of discrete samples as we going deep inside the timing graph and hence, results in exponential timing complexity. Therefore, in this paper we present novel deep neural network based operations which can accurately approximate the signal arrival-time's distributions with linear-time complexity. The various deep neural network (DNN) architectures have been used to implement both the maximum and the convolution operations using proper training dataset. Simulation results on various benchmark circuits (ISCAS 85, ISCAS 89, and ITC 99) show that the proposed method estimate the mean and standard deviation (STD) of critical path delay distribution with an average error of 0.75% and 2.56% as compared to Monte Carlo (MC), respectively. Our SSTA speeds up the traditional discrete approach by a factor of 20.7x on average. Furthermore, the PDF obtained from our method matches the ones obtained from MC with a reasonable error. Furthermore, we have proposed multi-wise maximum operations to reduce the arrival-time computational complexity at multi-inputs gates. Comparing to MC, the proposed method shows 0.97% and 2.58% average error in mean and STD respectively and the speeding up factor reaches 24.4x on average for all benchmarks.

VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models

In the advanced technology nodes, process parameter variations are increasingly resulting in unpredictable device behavior. The issue is even aggravated by low power requirements which stretches the transistor operation into near-threshold regime. Despite device simulation gives precise results, it is time-consuming for static timing analysis and dynamic timing analysis. In this paper, we propose VASTA, a statistical timing analysis tool based on the variation-aware standard cell library. The tool efficiently supports statistical static timing analysis (SSTA) and statistical dynamic timing analysis (SDTA). The standard cell library models delay under operating environment effects by using quadratic regressions and multivariate adaptive regression splines. VASTA works on industry formats (.v and.sdc) and is designed to run in parallel during both SSTA and SDTA. The statistical cell library is built and verified using SMIC 40 nm and 28 nm PDK. The mean and standard deviation errors of cell delay models are 2.77% and 1.68% compared with SPICE simulation results under 10k Monte Carlo samples. The SSTA and SDTA are tested with ISCAS85, ISCAS89, and EPFL benchmark suites. The average mean and standard deviation errors of SSTA are 4.01% and 2.03%, which are similar to SDTA. Meanwhile, our SDTA is 17.7 times faster than traditional corner-based dynamic timing analysis which relies on generating .vcd cell activity files.

Artificial neural network model for arrival time computation in gate level circuits

ABSTRACT Advances in the VLSI process technology lead to variations in the process parameters. These process variations severely affect the delay computation of a digital circuit. Under such variations, the various delays, i.e. net delay, gate delay, etc., are no longer deterministic. They are random in nature and are assumed to be probabilistic. They keep changing, based on factors such as process, voltage, temperature, and a few others. This calls for efficient tools to perform timing checks on a design. This work presents a technique to compute the arrival time of a digital circuit. The arrival time (AT) is computed using two different timing engines, namely, static timing analysis (STA) and statistical static timing analysis (SSTA). This work also aims to eliminate number of false paths. It uses a fast and efficient filtering method by utilizing ATPG stuck-at faults and path delay faults. ISCAS-89 benchmark circuits are used for implementation. The results obtained using the probabilistic approach are more accurate than the conventional STA. It has been verified with an Artificial Neural Network (ANN) model. The arrival time calculated using SSTA shows 7% improvement over that of STA. The absolute error is reduced twofold in the case of the ANN model for SSTA.

Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework

Negative bias temperature instability along with the presence of process variations has resulted in time-varying path criticalities. To ensure reliable circuit operation, aging sensors are used at the end of potential critical paths (PCPs) for delay monitoring. Optimization of the number of delay sensors requires accurate computational models for prediction of criticality and selection of PCPs. We identify a path as a PCP if its maximum global criticality over the lifetime exceeds a certain threshold. However, the global criticality of a path could vary nonmonotonically over the lifetime of the device. In this paper, we propose a framework for time-varying statistical static timing analysis (TV-SSTA), wherein the circuit delay is obtained as a collection of time-varying canonicals with breakpoints in time which define the end of validity of one and the start of the next canonical. We show that the global criticality of any path will be maximum either at $t = 0$ or at these breakpoints. Hence, criticality computation and PCP selection need to be done only at these time points, which typically is less than four. The TV-SSTA is integrated with a previously proposed criticality computation technique to identify the PCPs and the results are validated against Monte Carlo simulations.

Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis

Timing analysis is a key step in the digital design process. By modeling device delay variations statistical static timing analysis (SSTA) reduces pessimism compared to traditional static timing analysis (STA). However, it ignores the circuit’s logic which causes some timing paths to never, or only rarely, be sensitized. We introduce a general timing analysis approach and tool to calculate the probability that individual timing paths are sensitized, enabling the calculation of bounding delay distributions over all input combinations. We show how this analysis is related to the well-known #SAT problem and present approaches to improve scalability, achieving, on average, results 75% to 37% less pessimistic than STA while running 569 to 16 times faster than Monte-Carlo timing simulation.

Statistical Modeling of Combinational Circuits Using Path Based Delay Analysis

In nanometer regime, the variations in process parameters and environment parameters are increased radically which motivate the use of Statistical Static Timing Analysis (SSTA). In this paper, we propose a process and environment sensitivity based, SSTA algorithm for high speed CMOS technology combinational circuits. The algorithm calculates the propagation delay of the combinational circuits more correctly by considering all process parameters like length, width oxide thickness and dopant of the MOSFET and environment parameters like operating temperature and the supply voltage. To investigate the SSTA analyzer a combinational circuit application is used, namely four bit adder. The designed SSTA algorithm used more correct path based analysis instead of block base analysis. The accuracy of the model is verified using Monte Carlo analysis for 32 nm technology. The proposed SSTA method shows that the average errors 1.43% and 5.98% in mean and standard deviation, respectively compared with Monte Carlo analysis and need less simulation time than Monte Carlo analysis.

An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space

In this article, we present a critical path selection method that efficiently finds true (sensitizable) critical paths of a circuit in the presence of process variations. The method, which is based on the viability analysis, tries to select the least number of true critical paths that cover all of circuit critical gates. Critical gates are those that make a path critical with a probability higher than a predefined threshold value. Selecting fewer critical paths leads to less computation time for the algorithm and shorter test time of fabricated chips. For this purpose, an efficient Statistical Static Timing Analysis– (SSTA) based technique is suggested. This technique tries to find circuit-critical gates whose process parameter variations cover a major part of the process space. Improving the process space coverage using fewer paths is achieved by considering both spatial (proximity of gates) and structural (having common gates) correlations in the analysis of choosing the critical paths. In the selection process, paths with low similarities in their characteristics are preferred. In addition, only true paths whose delays affect the maximum delay of the circuit are included. The selected paths can be used in the test process of the fabricated chips to determine if the chip meets its timing requirements. Also, a modified viability analysis that incorporates statistical computations is used in the SSTA. The efficacy of the proposed method is evaluated by comparing its results for combinational and sequential ISCAS benchmarks with those obtained by exhaustive search. Results indicate although, on average, only 4.38% of all the critical paths found by the exhaustive search are selected by the proposed method, the maximum probability of criticality for the paths that are not considered in our method is, on average, less than 4%.

Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations

In this brief, we propose an effective adaptation of viability analysis in statistical static timing analysis. The adaption benefits well from a dynamic programming implementation of the viability function. For a rapid identification of statistical longest true paths, the technique makes use of a fast preprocessing step identifying the gates with a small probability of being viable in the circuit, and a number of simple optimization techniques. This makes the approach fast without lowering its accuracy. The efficacy of the proposed statistical timing analysis is assessed using ISCAS benchmark circuits and carry skip adders. The results show that the proposed technique leads to, on average, $18\times$ higher speed compared to those of the state-of-the-art technique. This improvement is achieved at the cost of −1.7% precision lost compared to that of the Monte-Carlo method.

Improved Statistical Static Timing Analysis Using Refactored Timing Graphs

Improved Statistical Static Timing Analysis Using Refactored Timing Graphs

A Skew-Normal Canonical Model for Statistical Static Timing Analysis

The use of quadratic gate delay models and arrival times results in improved accuracies for a parameterized block-based statistical static timing analysis (SSTA). However, the computational complexity is significantly higher. As an alternative to this, we propose a canonical model based on skew-normal random variables (SN model). This model is derived from the quadratic canonical models and can consider the skewness in the gate delay distribution as well as the nonlinearity of the MAX operation. Based on conditional expectations, we derive the analytical expressions for the moments of the MAX operator and the tightness probability that can be used along with the SN canonical models. The computational complexity for both timing and criticality analysis is comparable with SSTA using linear models. There is a two to three orders of magnitude improvement in the run time as compared with the quadratic models. Results on ISCAS benchmarks show that the SN models have a lower variance error than the quadratic model, but the error in the third moment is comparable with that of the semiquadratic model.

GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis

As the semiconductor technology node scales into the deep submicrometer regime, it has become very difficult to obtain high IC yields because the process–voltage–temperature variations induce large spreads in delay and power. In this paper, we propose a new framework, called GenFin, which is, as far as we know, the first to target the multiobjective yield optimization of logic circuits. Since FinFETs are a promising substitute for CMOS at 22-nm technology node and beyond, we evaluate the framework with a 22-nm FinFET logic library. By combining the power of genetic algorithm (GA) and adaptive multiobjective optimization, GenFin produces a set of nondominated logic circuits whose timing, leakage power, and dynamic power yields are simultaneously optimized. This can help designers make tradeoff decisions wisely and avoid suboptimal solutions. We also propose an incremental statistical circuit analyzer, called incremental FinPrin, that speeds up the statistical static timing analysis by up to $9.6\times $ and the statistical power analysis by up to $2235.7\times $ , while incurring errors of only up to 0.031% in mean and 0.74% in standard deviation relative to nonincremental analysis. We use heuristics based on the deterministic timing analysis and gate criticality to reduce the GA search space and also improve the quality of its solutions. We present extensive experimental results to demonstrate the efficacy of GenFin.

Efficient Statistical Timing Analysis Using Deterministic Cell Delay Models

This brief presents an efficient approach to statistical static timing analysis (STA), which estimates the system delay of statistical STA through deterministic STA. In statistical STA, the system delay is modeled as a function of random variables, so it is commonly expressed as a probability density function (pdf). Therefore, to estimate the system delay of statistical STA through deterministic STA, we must find the relationship between an arbitrary percentile point on the pdf of the system delay and the gate delays used in deterministic STA. However, there is no closed-form equation for an arbitrary percentile point on the pdf of the system delay, we derive an analytic expression for the upper bound of an arbitrary percentile point on the pdf of the system delay. This allows us to obtain the corresponding gate delays that are used to estimate the upper bound of the percentile point on the pdf of the system delay through deterministic STA. Experimental results indicate that the percentile point on the pdf of the system delay obtained with statistical STA is strictly bounded by the upper bound of the percentile point obtained with the proposed method within an average 6% difference range.

Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation

Nanoscale VLSI systems are subject to increasingly significant performance variability. Accurate timing analysis and effective silicon-based performance verification techniques are critical to successful nanoscale VLSI design. The state-of-the-art statistical static timing analysis (SSTA) techniques cannot capture performance variability due to primary inputs and sequential element states which, however, is critical to path delay test generation. In this paper, we present the first dynamic statistical timing analysis-based VLSI path delay test pattern generation technique. We observe that VLSI timing analysis and power estimation target the same signal toggling activity. By leveraging the existing power estimation techniques, we have developed signal-probability-based statistical timing analysis (SPSTA), and SPSTA-based VLSI delay test pattern generation (SPSTA-DTPG) techniques. Our experimental results based on ISCAS’89 benchmark circuits show that the state-of-the-art statistical static timing analysis-based delay test pattern generation (SSTA-DTPG) achieves an average of 47.32%, 45.14%, and 57.98%, SPSTA-DTPG achieves an average of 57.41%, 61.43%, and 68.05%, while signal probability-based statistical timing analysis-based delay test pattern generation with (test pattern) compaction (SPSTA-DTPG-C) achieves an average of 83.09%, 87.48% and 90.30% coverage of the top 50, 100, and 200 timing-critical paths, respectively.