Static Test Compaction Procedure Research Articles

Broad-Brush Compaction for Sequential Test Generation

Test sequences that do not use scan chains have several advantages as manufacturing tests. Test sequences can be produced by sequential test generation procedures, and static test compaction can be applied to reduce the length of the sequence without losing fault coverage. A typical sequential test generation procedure that produces a single test sequence concatenates test subsequences to form the test sequence. Existing static test compaction procedures ignore the construction of the sequence from subsequences and consider every test vector individually for omission. This brief introduces a broad-brush static test compaction procedure that considers entire subsequences for omission to achieve test compaction. As additional subsequences are concatenated, subsequences concatenated earlier may become unnecessary. The procedure described in this brief identifies this situation. The advantage of a broad-brush approach is a low computational effort, which is demonstrated by experimental results for benchmark circuits.

Skewed-Load Tests for Transition and Stuck-at Faults

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure.

Static test compaction procedure for large pools of multicycle functional broadside tests

This study describes a static test compaction procedure that is applicable in the scenario where (i) a large pool of tests can be generated efficiently, but (ii) test compaction that modifies tests, and covering procedures, are not applicable, and (iii) reverse order fault simulation procedures are not sufficient for test compaction. The procedure has the ability to identify tests in the pool that are effective for test compaction even when they do not increase the fault coverage. This ability is achieved using only fault simulation with fault dropping. The procedure is designed for the case where multicycle functional broadside tests are extracted from functional test sequences. The use of multicycle tests results in higher levels of test compaction than possible with two-cycle functional broadside tests. It adds another dimension to the procedure that also needs to select a number of clock cycles for every test.

Static test compaction for circuits with multiple independent scan chains

This study describes a static test compaction procedure for transition faults in circuits with multiple scan chains where each scan chain can operate independently in functional or shift mode. The procedure mixes parts of different broadside and skewed-load tests, where the parts coincide with the scan chains, in order to create new tests that detect more faults. This allows the number of tests to be reduced without reducing the fault coverage. By mixing parts of tests with different types, different scan chains are assigned different modes of operation within the same test. Experimental results are presented to demonstrate that this allows the number of tests to be reduced below the number of tests in a compact test set that consists of broadside and skewed-load tests.

Test Vector Omission for Fault Coverage Improvement of Functional Test Sequences

Test vector omission was introduced as a static test compaction procedure for functional test sequences. Experimental results indicated that it can also increase the fault coverage accidentally when it is applied to a sequence that does not detect all the detectable target faults. However, this capability was not explored directly. It is important since test vector omission provides a smaller search space for functional test sequences than any existing approach to sequential test generation. This paper describes a branch-and-bound procedure for test vector omission whose goal is to find functional test sequences for faults that are not detected by a given sequence. Experimental results for benchmark circuits demonstrate that the procedure provides a cost-effective addition to a simulation-based sequential test generation procedure.

Two-Dimensional Static Test Compaction for Functional Test Sequences

A restoration based static test compaction procedure removes unnecessary test vectors from a functional test sequence in order to reduce its length. To allow the procedure to reduce the storage requirements of the sequence further, this paper introduces a new approach where a single stored sequence is used for applying several different functional test sequences. Under this approach, the stored sequence is considered as two-dimensional arrays with different dimensions. Each array yields a different test sequence, which is a permutation of the stored sequence. When the permutations are effective in detecting target faults, an existing static test compaction procedure, with certain modifications, can reduce the length of the stored sequence, and rely on the application of the permutations to detect all the target faults. Simulation results show significant reductions in the input test data volume. The cost of increased numbers of clock cycles for test application can be utilized for increasing the fault coverage of non-target faults.

Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity

This brief describes a static test compaction procedure for low-power test sets, which is based on the observation that a higher switching activity leads to a smaller number of tests. To use this observation in the context of low-power test sets, this brief makes the following new observations. First, considering the number of tests in a given test set where a line $g$ makes a $0 \rightarrow 1$ or a $1 \rightarrow 0$ transition, there are large variations in this number between different lines. Increasing the switching activity only for a subset $G$ of lines that make the smallest numbers of signal transitions is sufficient for achieving test compaction. Second, the switching activity for the subset $G$ can be increased in a way that the specific values that the lines assume can occur during functional operation, and the maximum switching activity for the test set does not increase. These observations allow the compacted test set to remain a low-power test set. Experimental results demonstrate significant reductions in the numbers of tests in low-power test sets for transition faults in benchmark circuits.

A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences

A class of static test compaction procedures for functional test sequences is based on the omission of unnecessary test vectors. According to the definition used by these procedures, a test vector is unnecessary if all the target faults continue to be detected after it is omitted. This article introduces a more general definition of unnecessary test vectors that allows additional ones to be omitted. According to this definition, a test vector is unnecessary if every target fault can be detected by a sequence that is obtained after omitting the vector, and possibly other vectors. The article develops a procedure for omitting test vectors based on this definition and discusses its effects on the storage requirements and test application time.

Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks

An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. A transparent-scan sequence for one block is likely to detect faults in other blocks since transparent scan does not distinguish between functional and scan clock cycles, and allows faults to be detected at all the clock cycles of the sequence. Such sharing of tests is not meaningful with conventional scan-based tests, especially when the blocks have different numbers of state variables. Transparent scan thus enhances the ability to produce a compact test set for a group of logic blocks. The static test compaction procedure described in this paper uses transparent-scan sequences that follow the application of conventional scan-based tests precisely. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it selects a subset that detects all the target faults, which are detected by the complete set.

Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences

The goal of static test compaction is to reduce the number or tests, or the lengths of test sequences, without reducing the fault coverage. Static test compaction that reduces the number of tests was formulated as a set covering problem in order to benefit from the heuristics that exist for solving this problem. This paper applies set covering concepts and heuristics to static test compaction that reduces the length of a functional test sequence. Although set covering is not applicable directly to a single test sequence, it provides a theoretical framework and justification for a particular set of heuristics. The procedure uses a parameter denoted by n to determine the computational effort for computing the sets that are used for making compaction decisions. With n=1, the procedure is equivalent to a static test compaction procedure that does not use set covering. Experimental results demonstrate that shorter test sequences are obtained for n>1 than for n=1. A variation of the static test compaction procedure that produces a monotonic decrease in test sequence length with n is also described.

Static test compaction for mixed broadside and skewed‐load transition fault test sets

Test sets that consist of both broadside and skewed-load tests provide improved delay fault coverage for standard-scan circuits. This study describes a static test compaction procedure for such test sets. The unique feature of the procedure is that it can modify the type of a test (from broadside to skewed-load or from skewed-load to broadside) if this contributes to test compaction. Given a test set W, the basic static test compaction procedure described in this study considers for inclusion in the compacted test set both a broadside and a skewed-load test based on every test w ∈ W. It selects the test type that detects the higher number of faults. An improved procedure considers a broadside and a skewed-load test based on a test w ∈ W only if w detects a minimum number of faults (without changing its type). Experimental results demonstrate that the static test compaction procedure is typically able to reduce the sizes of mixed test sets further than a procedure that does not modify test types. The procedure modifies the types of significant numbers of tests before including them in the compacted test set.

On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests

Multicycle (multipattern) scan-based tests contain multiple clock cycles between scan operations. Each such clock cycle defines a pattern of the test. Multipattern tests require fewer clock cycles for test application compared with single-pattern or two-pattern tests for the same target faults. In addition, this paper demonstrates that patterns appearing later in a test typically have lower switching activity than patterns appearing earlier in the test. Based on these observations, the paper presents a static test compaction procedure for multipattern tests that targets a reduction in switching activity while reducing the number of clock cycles required for test application. The procedure is based on an operation called test merging. Merging of a test pair causes the patterns from both tests to appear in a single test. By placing the patterns from a test with a high switching activity at the end of a merged test, their switching activity can be reduced. The proposed procedure combines the test merging procedure with a procedure that modifies a test set so as to reduce its switching activity. Through this procedure it takes advantage of the opportunities created by test merging to reduce the switching activity of patterns that appear later in a test.

Static test compaction for diagnostic test sets of full-scan circuits

The authors describe a static test compaction procedure for diagnostic test sets of full-scan circuits. Similar to reverse order and random order fault simulation procedures applied to fault detection test sets, the procedure simulates the test set in different orders in order to identify unnecessary tests. Two features distinguish the procedure from earlier ones. (i) It uses a diagnostic fault simulation process based on equivalence classes to identify tests that are not necessary for distinguishing fault pairs. (ii) It includes an iterative reordering process whose goal is to increase the number of tests that will be identified as unnecessary. Experimental results are presented to demonstrate the ability of the procedure to compact diagnostic test sets and the effectiveness of the iterative reordering process.

Vector replacement to improve static-test compaction for synchronous sequential circuits

Static-test compaction procedures for synchronous sequential circuits may saturate and be unable to further reduce the test-sequence length before the test length reaches its minimum value, resulting in test sequences that may be longer than necessary. We propose a method to take a static-compaction procedure out of saturation and allow it to continue reducing the test-sequence length. The proposed method is based on the replacement of test vectors in the test sequence every time the compaction procedure reaches saturation. Test-vector replacement is done such that the fault coverage of the sequence is maintained. Experimental results using an effective static-compaction procedure demonstrate that reductions in test length can be obtained by the proposed vector replacement method.

Static test compaction for synchronous sequential circuits based on vector restoration

We propose a new static test compaction procedure for synchronous sequential circuits. The procedure belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its length without reducing the fault coverage. The previous procedure that achieved high levels of compaction using this approach attempted to omit test vectors from a given test sequence one at a time or in subsequences of consecutive vectors. The omission of each vector or subsequence required extensive simulation to determine the effects of each omission on the fault coverage. The procedure proposed here first omits (almost) all the test vectors from the sequence, and then restores some of them as necessary to achieve the required fault coverage. The decision to restore a vector requires simulation of a single fault. Thus, the overall computational effort of this procedure is relatively low. The loss of compaction compared to the scheme that omits the vectors one at a time or in subsequences is small in most cases. Techniques to speed up the restoration process are also investigated, including consideration of several faults in parallel during restoration, and the use of a parallel fault simulator. Experimental results are presented to demonstrate the effectiveness of vector restoration as a static compaction technique.