Static Random Access Memory Memory Research Articles

An efficient unused integrated circuits detection algorithm for parallel scan architecture

In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm.

Design and VLSI implementation of SRAM memory array using Application-specific Integrated circuits design flow

Abstract Static Random-access memory (SRAM) are useful structure blocks in operations like data storage, embedded operations, cache recollections, microprocessors. The circuits should retain larger impunity to noise voltages. So, the Stationary Noise Margin (SNM) of the circuits should be veritably high. Large SRAM arrays that are extensively used as cache memory in microprocessors and operation-specific integrated circuits can absorb a big portion of the chip area. Highly compact circuits like SRAM arrays are estimated to cover relatively 90% of the System on chip area within the coming years. To optimize the performance of similar chips, large arrays of fast SRAM help to speed up the system performance. As a result, numerous minimal-size SRAM cells are tightly packed making SRAM arrays the compact circuitry on a chip. In this work an attempt is made to design a 8 X 8 SRAM memory array along with different components like Write driver circuit, Pre-charge circuit, Row and Column Decoder. Different SRAM architectures such as 6T, 7T and 8T are designed and different parameters such as Static Noise Margin and power dissipated are measured and the best performing memory design has been selected. 8T design has been resulted with least power dissipation. Hence this cell is selected for designing the memory array. A schematic of 8 x 8 array is designed and the layout of single SRAM 8T is created and to complete the ASIC design flow, DRC is done and the pre and post simulation are compared and verified. The integrated SRAM is operated with an input voltage of 0 to 1.8V.

Performance Evaluation of Different Topologies of SRAM and SRAM Memory Array Design at 180nm Technology

Memory circuits such as static random-access memory (SRAM) and dynamic random-access memory (DRAM) form an integral part of system design and contribute significantly to system-level power consumption. Memory operating speeds and power dissipation have become important parameters due to the explosive growth of battery-operated appliances and the increased integration of circuits Hence SRAMs with different topologies are examined in terms of parameters like propagation delay, Static Noise Margin (SNM), corner analysis, and static power dissipation by simulating using versatile tool cadence virtuoso at 180nm technology. Besides, topological performance comparison, the SRAM memory array has also been illustrated from 2×2, 4×4 to 8×8, thereby verifying the read and write modes of operation of SRAM.

A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2.

An 8kb RRAM-Based Nonvolatile SRAM with Pre-Decoding and Fast Storage/Restoration Time

Combining the advantages of low-power consumption of static random access memory (SRAM) with high stability and nonvolatile of resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell was proposed in this paper. In order to solve the problem that data cannot be stored when SRAM is powered off, RRAM technology was introduced into SRAM to realize an SRAM with nonvolatile function. The differential mode was adopted to improve the data restoration speed. Meanwhile, a pre-decoding technology was proposed to realize fast address decoding, and a voltage-mode sensitive amplifier was used to achieve fast amplification of two bit lines, so as to improve the reading speed of the memory. An 8kb nvSRAM was implemented with a CMOS 28 nm 1P9M process. The simulation results show that when the power supply voltage was 0.9 V, the static/read/write noise margin was 0.35 V, 0.16 V and 0.41 V, respectively. The data storage time was 0.21 ns, and restoration time was 0.18 ns. The time for the whole system to read 1 bit of data was 5.2 ns.

COCKTAIL: Multicore Co-Optimization Framework With Proactive Reliability Management

High performance computing (HPC) servers aim to meet an increase in the number and complexity of tasks and, consequently, to address the energy efficiency challenge. In addition to energy efficiency, it is essential to manage lifetime limitations of power-hungry components of servers (e.g., cores and cache), hence avoiding server failure before its lifetime period. Traditional approaches focus on either using hybrid caches to reduce the leakage power of traditional static random-access memory (SRAM) cache, and thus increase the energy efficiency, or the trade-off between the lifetime and performance of multi-core processors. However, these approaches fall short in terms of flexibility and applicability for HPC tasks in terms of multi-parametric optimization including quality-of-service (QoS), lifetime reliability, and energy efficiency. As a result, in this paper we propose COCKTAIL, a holistic strategy framework to jointly optimize the energy efficiency of multi-core server processors and tasks performance in the HPC context, while guaranteeing the lifetime reliability. First, we analyze the best cache technology among traditional SRAM and resistive random access memory (RRAM), within the context of hybrid cache architectures, to improve the energy efficiency and manage cache endurance limits with respect to tasks requirements. Second, we introduce a novel efficient proactive queue optimization policy to reorder HPC tasks for execution considering their end time and possible reliability effects on the use of the hybrid caches. Third, we present a dynamic model predictive control (MPC)-based reliability management method to maximize task performance, by controlling the frequency, temperature, and target lifetime of the server processor. Our results demonstrate that, while consuming similar energy, COCKTAIL provides up to 60% QoS improvement when compared to latest state-of-the-art energy optimization and reliability management techniques in the HPC context. Moreover, our strategy guarantees a design lifetime longer than 5 years for the whole HPC system.

Design of Low Power and Failure Free SRAM Cell Using Read Assist Circuits

Static Random Access Memory (SRAM) is one of the main peripherals in all the Very-large-scale Integrated (VLSI) chips, which enact a vital part in all executable applications. The write ability and read stability are prime factors with low power supply and improve operation speed with temperature, process, and voltage variations. In VLSI design, the System on Chip (SoC) performance is improved by applying low power supply and change in few Pico seconds of cycle times or memory access. The read/write operation is not accurate in lower supply voltage because it will not flip to the desired voltage levels. For improving performance, proposed an SRAM cell to flip to the desired voltage levels to reduce readability failures in low supply voltages. The additional requirement is needed to increase the chip’s performance with lower supply voltages, and continuously additional circuit techniques are needed for obtaining the SRAM memory’s readability and writing ability. In this paper, different performance improvement methods of SRAM memory cells are analyzed. The reduced word line voltage read assist circuit is designed for the SRAM memory cell.

FinFET based SRAMs in Sub-10nm domain

An exponential rise in transistor count, have increased the power consumption of the modern digital system. Moreover, at lower technology node, the performance of conventional CMOS designs degrades because of the short channel effects (SCEs). In sub-10 ​nm technologies, FinFET devices have good gate control and achieve superior performance than CMOS designs. FinFET devices possess high ION current and improved scalability compared to conventional CMOS. Among numerous double gate (DG) devices, the quasiplanar FinFET structure gained huge attention because of the simple fabrication process [4]. However, FinFET based designs have a major width quantization issue. The width of FinFET device varies only in quanta of silicon fin height (HFIN) [4]. This is a critical issue for ratioed designs like Static Random-Access Memory (SRAMs), where proper sizing of transistors is essential for correct functionality. With process variations, this issue becomes even worse and affect the performance of SRAM cell. The SRAM has a significant performance impact on current nanoelectronics systems. Next-generation devices overcome the short-channel effects (SCE) of CMOS technology and can be used to improve the efficiency of SRAM designs. FinFETs are promising emerging devices, which can improve the performance of SRAM designs at lower technology nodes. This review paper presents different types of SRAM bitcells and memory system architectures. It also discusses the detailed analysis of SRAM bitcells based on various highly explored FinFET devices in sub-10nm domain. The read stability and write ability of SRAM cells are determined using Static Noise Margin (butterfly) and N-curve methods. Moreover, this manuscript presents a benchmarking between the Underlapped FinFET based SRAM and Design Technology Optimized FinFET Based SRAM. In addition to this, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations to determine the robustness of SRAM designs. Simulations were done in HSPICE using 7 ​nm technology.

Design of low power, variation tolerant single bitline 9T SRAM cell in 16-nm technology in subthreshold region

The major design parameters of embedded cache memory (SRAM memory cell) are speed, power consumption, noise tolerance, and reliability. It is a challenging task to design an SRAM cell in the face of process, voltage, and temperature variations at low supply voltages. At scaled technology node the conventional 6T SRAM cell suffers from read and write failures as well as instability. Moreover, it is susceptible to multibit soft error rate since it does not support bit-interleaving architecture. This paper proposes a low-power robust single bitline 9T (nine transistor) SRAM (Static Random Access Memory) at a 16-nm technology node in the subthreshold region. The potency of the proposed cell is shown by comparing it with other recently published SRAM cells, namely, single-ended NTV 9T (SENTV9T), write and read enhanced 9T (WREN9T), and the conventional 6T (CONV6T) SRAM cells. The proposed cell provides 1.25×/1.96 × lower read current IREAD variability compared with WREN9T/SENTV9T. The proposed cell achieves 4.23 × higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with CONV6T due to the fact that it employs read decoupled operation. Moreover, SBL9T consumes lower standby power during hold state and dynamic power in the active state as compared with SENTV9T, WREN9T, and CONV6T. SBL9T also exhibits 10.01×/8.65×/11.47× narrower spread in standby power compared with CONV6T/WREN9T/SENTV9T. The dynamic power spread shows a similar trend with SBL9T providing 1.97×/1.02× narrower spread in dynamic power compared with WREN9T/SENTV9T. These benefits however are achieved by the SBL9T at the cost of 1.28×/0.71×/1.01× longer read delay compared with CONV6T/WREN9T/SENTV9T.

Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure.

Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers, benefiting from noisy SRAM cells whose start-up values flip between different power-on cycles. Embarking from this phenomenon, a novel performance (i.e., randomness and throughput) improvement method of SRAM-based TRNG is proposed, and its implementation can be divided into two phases: irradiation exposure and hardware postprocessing. As the randomness of original SRAM power-on values is fairly low, ionization irradiation is utilized to enhance its randomness, and the min-entropy can increase from about 0.03 to above 0.7 in the total ionizing irradiation (TID) experiments. Additionally, while the data remanence effect hampers obtaining random bitstreams with high speed, the ionization irradiation can also weaken this impact and improve the throughput of TRNG. In the hardware postprocessing stage, Secure Hash Algorithm 256 (SHA-256) is implemented on a Field Programmable Gate Array (FPGA) with clock frequency of 200 MHz. It can generate National Institute of Standards and Technology (NIST) SP 800-22 compatible true random bitstreams with throughput of 178 Mbps utilizing SRAM chip with 1 Mbit memory capacity. Furthermore, according to different application scenarios, the throughput can be widely scalable by adjusting clock frequency and SRAM memory capacity, which makes the novel TRNG design applicable for various Internet of Things (IOT) devices.

Flexible Resistive Switching Memory Devices Based on Graphene Oxide Polymer Nanocomposite

Flexible resistive switching memory devices based on graphene oxide (GO) polymer nanocomposite were prepared on flexible substrate to research the influence of bending on resistive switching behavior. The devices showed evident response in resistive switching memory characteristics to flexible bending. The 2000 cycles flexible bending leads to the switch of resistive switching memory characteristic from write-once-read-many time memory (WORM) to static random access memory (SRAM). Both WORM and SRAM memory properties are all repeatable, and the threshold switching voltage also showed good consistency. The resistive switching mechanism is attributed to the formation of carbon-rich conductive filaments for nonvolatile WORM characteristics. The bending-induced micro-crack may be responsible for the partial broken of the electrical channels, and may lead to the volatile SRAM characteristics.

Hybrid on-chip soft computing model for performance evaluation of 6T SRAM cell using 45-nm technology

A hybrid on-chip approach based on the variants of soft computing techniques is proposed in this work to evaluate the performance metrics of a 6T static random access memory (SRAM) cell in 45-nm technology. The performance metric evaluated for the SRAM cell is the data retention voltage (DRV) with optimal memory requirements. Each of the SRAM memory cells intends the chip to possess low density but operates at high speed. This paper formulates a hybrid soft computing framework comprising a deep backpropagation neural network which trains the fuzzy inference system to determine the performance metrics of 6T SRAM cell. The weight and bias parameters of the deep learning neural framework are optimized through a cat swarm optimization algorithm so as to reduce the elapsed convergence time of the new hybrid soft computing model. Evaluation process is executed based on the driven outputs from deep learning model to the fuzzy inference system (FIS) module so as to achieve the best values of DRV. Data retention voltage plays a major role in reducing the substantial leakage current and static noise margin intends to retain the data without losing them. Deep backpropagation neural network gets trained with deep learning procedures and optimizes the rule parameters and membership parameters of the FIS design structure. The performance metric DRV under various constraints prove to be better and effective in comparison with the solutions from the existing literature works for the same configuration of 6T SRAM cell using 45-nm technology.

A Low Power 6T-Auto Awake Mode-SRAM Design for high speed storage application

In the digital world, Static Random Access Memory (SRAM) is one of the efficient core component for electronics design, it consumes huge amount of power and die area. In this research, the SRAM design analysis in terms of read margin, write margin and Static Noise Margin (SNM) for low power application is considered. In SRAM memory, both read and write operation affect by noise margin. So, read and write noise margins are considered as the significant challenges in designing SRAM cell. In this research, robust 6T-SRAM cell is designed to decrease the power utilization. The Auto Awake Mode is developed to control the entire 6T-SRAM cell design. The proposed 6T-SRAM- Auto Awake Mode (6T-SRAM-AAM) was implemented to reduce power utilization of understand and write down operation inside the 20 nm FinFET library. The experimental results showed the proposed 6T-SRAM-AAM design reduced power consumption of read & write operation up to 25% to 33.33% compared to existing Static RAM cells design.

Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder

Wide-spread availability of high-speed INTERNET and rapid increase of smart-phone users have significantly increased online video surfing. Video decoders like H.264/H.265/MPEG consume a significant amount of power in Static Random Access Memory (SRAM) buffers. In this study, the authors propose a 1 kb (32 × 32) heterogeneous 8T SRAM architectures with (2-lower order bits) and without truncation for H.264 video decoder. They have used heterogeneous sized SRAM design and bit-truncation techniques are used simultaneously to obtain low power memory design for the H.264 video decoder. They show that the proposed approximate memory used for H.264 video decoder provide high video quality even at low power and low area budget of 0.3 µW/pixel and 5.2 µm 2 /pixel, respectively, at 0.5 V and 20 MHz in UMC 28 nm CMOS technology. The proposed memory architecture is compared with existing approximate memories such as heterogeneous 6T, hybrid 8T/6T, all-identical 6T, and all-identical 8T SRAM memory. The results show that proposed memory architectures perform cumulatively better than existing techniques in terms of dynamic power, leakage power, and area.

Impact of Total Ionizing Dose on Low Energy Proton Single Event Upsets in Nanometer SRAM

The impact of the total ionizing dose (TID) on a low energy proton single event upset (SEU) in a 65-nm static random access memory (SRAM) is investigated based on a low energy proton accelerator. The body potential of the P-well is elevated due to charge depletion along the sidewall of shallow trench isolation (STI) induced by TID irradiation. The radiation-induced narrow channel effect causes a decrease in the area and the thickness of the SEU sensitive volume (SV), further resulting in the low energy proton SEU cross section being lowered in 65-nm SRAM with an external independent power supply of the memory array. The impact of the TID on the low energy proton SEU cross section is dependent on test patterns written to the memory array during TID irradiation and SEU testing. The low energy proton SEU cross section is the highest when the complement test pattern is written to the SRAM memory array during TID irradiation and SEU testing compared with the same and half complement patterns.

Energy Efficient Single-Ended 6-T SRAM for Multimedia Applications

Image processing and other multimedia applications require large embedded storage. In some of the earlier works approximate memory has been shown as a potential energy-efficient solution for such error-tolerant applications. In this brief, we propose a single ended 6-T (SE6T) static random access memory (SRAM) cell which has about 50% less dynamic power compared to conventional 6-T SRAM cell with the same bit error rate (BER). Since image processing applications are tolerant to errors, ultra low voltage power-efficient embedded memories with BER can be used for storage. We show that 1 KB ( $256 \times 32$ ) SE6T memory consumes $ {0.45\times }$ dynamic power, $ {0.83\times }$ leakage power and takes $ {0.60\times }$ area as compared to conventional 6T SRAM memory for similar peak signal to noise ratio (PSNR). We have also proposed heterogeneous SE6T 1K SRAM memory and show that for a given power budget, PSNR enhances by at least by 14 dB compared to when homogeneous (identically sized bit-cells) SE6T SRAM memory are used. When compared with heterogeneous 6T SRAM memory, the heterogeneous SE6T SRAM memory consumes $ {0.44\times }$ dynamic power, $ {0.86\times }$ leakage power and takes $ {0.6\times }$ area for almost similar PSNR. For a given PSNR, the SE6T memory is cumulatively better in terms of design complexity, area and power when compared with other hybrid and heterogeneous approximate memories.

Secret Key Generation Over Biased Physical Unclonable Functions With Polar Codes

Internet-of-Things (IoT) devices are usually small, low cost, and have limited resources, which makes them vulnerable to physical and cloning attacks. To secure IoT devices, physical unclonable functions (PUFs) are relatively new security primitives used for device authentication and device-specific secret-key generation. In this paper, we focus on designing a robust construction to derive secret keys from static randomaccess memory (SRAM)-PUFs, which enjoy the uniqueness and randomness properties stemming from the manufacturing variations of SRAM memory cells. We make use of a polar code construction. Based on the fact that SRAM memory can often be found in today's IoT devices, and since polar codes have been selected as error-correction technique in the fifth generation standard, this makes the proposed scheme a promising candidate for reducing the extra cost and securing resource-constrained IoT devices. In this paper, we propose a novel construction method to eliminate the effect of noise and bias in SRAM-PUFs. We shall prove that the secrecy leakage of the helper data about the secretkey can be made negligible due to polarization and proper code construction design. Results show that the proposed scheme provides a significant improvement of the reliability (achieve a failure probability below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> ) and of the realizable secret-key rate, which is also evaluated by the theoretical analysis. In addition, the proposed scheme provides the possibility to tradeoff complexity, secrecy, and reliability with the same code construction for different IoT applications.

EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA

Ternary content-addressable memories (TCAMs) are used to design high-speed search engines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and field-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs) platforms but both have the drawback of high power consumption. This paper presents a pre-classifier-based architecture for an energy-efficient SRAM-based TCAM. The first classification stage divides the TCAM table into several sub-tables of balanced size. The second SRAM-based implementation stage maps each of the resultant TCAM sub-tables to a separate row of configured SRAM blocks in the architecture. The proposed architecture selectively activates at most one row of SRAM blocks for each incoming TCAM word. Compared with the existing SRAM-based TCAM designs on FPGAs, the proposed design consumes significantly reduced energy as it activates a part of SRAM memory used for lookup rather than the entire SRAM memory as in the previous schemes. We implemented the proposed approach sample designs of size 512 × 36 on Xilinx Virtex-6 FPGA. The experimental results showed that the proposed design achieved at least three times lower power consumption per performance than other SRAM-based TCAM architectures.

Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

Tuning Electrical Memory Behavior from Nonvolatile to Volatile by Varying Tethering Positions of the Anthracene Moiety in Functional Polyimides

In this work, three functional polyimides, in which the diaminophenylaminoanthracene (DAPAA) group served as the electron donor and 4,4′-hexafluoroisopropylidene dianhydride (6FDA) served as the electron acceptor, were synthesized and denoted as 1-DAPAA-6FDA, 2-DAPAA-6FDA, and 9-DAPAA-6FDA. The only difference between the three polyimides was that the anthracene group in DAPAA was attached to the nitrogen atom through different tethering positions (1-, 2-, and 9-). Characterization results indicate that the 1-DAPAA-6FDA and 9-DAPAA-6FDA based memory devices exhibit nonvolatile write once read many times memory (WORM) behavior, while the 2-DAPAA-6FDA based memory device exhibits volatile static random access memory (SRAM) behavior. Quantum chemical calculation results indicate that a lower dihedral angle between the anthracene group and the molecular backbone of 2-DAPAA-6FDA caused better coplanar structure for charge transfer (CT) and back CT processes, which accounts for the observed volatile SRAM memory performance. All of the polyimides possess excellent long-term operational stability. This work reveals the possibility of tuning memory behavior by elaborately adjusting the spatial conformation of the electron donor, providing feasible guidance for the design of polymer memory materials.