Static Random Access Memory Chips Research Articles

A Noninvasive Technique to Detect Authentic/Counterfeit SRAM Chips

Many commercially available memory chips are fabricated worldwide in untrusted facilities. Therefore, a counterfeit memory chip can easily enter into the supply chain in different formats. Deploying these counterfeit memory chips into an electronic system can severely affect security and reliability domains because of their substandard quality, poor performance, and shorter lifespan. Therefore, a proper solution is required to identify counterfeit memory chips before deploying them in mission-, safety-, and security-critical systems. However, a single solution to prevent counterfeiting is challenging due to the diversity of counterfeit types, sources, and refinement techniques. Besides, the chips can pass initial testing and still fail while being used in the system. Furthermore, existing solutions focus on detecting a single counterfeit type (e.g., detecting recycled memory chips). This work proposes a framework that detects major counterfeit static random-access memory (SRAM) types by attesting/identifying the origin of the manufacturer. The proposed technique generates a single signature for a manufacturer and does not require any exhaustive registration/authentication process. We validate our proposed technique using 345 SRAM chips produced by major manufacturers. The silicon results show that the test scores ( F 1 score) of our proposed technique of identifying memory manufacturer and part-number are 93% and 71%, respectively.

Data Sanitization of SRAM by Thermal Distortion

Thermal distortion of a memory state is demonstrated for data sanitization of static random access memory (SRAM). Data stored in SRAM are believed to be deleted when power is turned off. However, it has been reported that the data can remain for a certain time even in powered- OFF SRAM, especially in a low-temperature environment. When a cold boot attack is attempted at low temperature, the stored data in SRAM are secured by thermal distortion at induced high temperature. For an experimental demonstration of data sanitization, heat is intentionally applied to a commercial SRAM chip, which is connected with a Raspberry pi board to write and read data. Supportive circuit and thermal simulations are performed to analyze electrical and thermal characteristics during heat treatment.

Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure.

Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers, benefiting from noisy SRAM cells whose start-up values flip between different power-on cycles. Embarking from this phenomenon, a novel performance (i.e., randomness and throughput) improvement method of SRAM-based TRNG is proposed, and its implementation can be divided into two phases: irradiation exposure and hardware postprocessing. As the randomness of original SRAM power-on values is fairly low, ionization irradiation is utilized to enhance its randomness, and the min-entropy can increase from about 0.03 to above 0.7 in the total ionizing irradiation (TID) experiments. Additionally, while the data remanence effect hampers obtaining random bitstreams with high speed, the ionization irradiation can also weaken this impact and improve the throughput of TRNG. In the hardware postprocessing stage, Secure Hash Algorithm 256 (SHA-256) is implemented on a Field Programmable Gate Array (FPGA) with clock frequency of 200 MHz. It can generate National Institute of Standards and Technology (NIST) SP 800-22 compatible true random bitstreams with throughput of 178 Mbps utilizing SRAM chip with 1 Mbit memory capacity. Furthermore, according to different application scenarios, the throughput can be widely scalable by adjusting clock frequency and SRAM memory capacity, which makes the novel TRNG design applicable for various Internet of Things (IOT) devices.

Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor

The robustness of Static random access memory (SRAM) Physical unclonable functions (PUFs) is threatened by the state change of the power-up value (R) at different temperatures. The voltage ramp-up time Tramp is one of the factors that can affect the stability of R. Some studies have been performed on the Tramp of commercial SRAM chips at the microsecond (μs) level. In this paper, a robust and low cost SRAM PUF using a p-channel metal oxide semiconductor (PMOS) as a power switch to enhance the stability of R is proposed. Tramp is as fast as 11 V/ns. The proposed SRAM PUF has a linear shift register extractor, with an extraction rate as high as 7/18 and no helper data in contrast to traditional von Neumann extractor. This chip has been fabricated using 0.11 μm ultra-low-leakage technology. The experiment results show that R becomes stable at [-40 °C, 85 °C], and a simple lightweight error correcting codes (ECC) can be used in SRAM PUF.

SCARe: An SRAM-Based Countermeasure Against IC Recycling

With the rapid growth of the electronics market, counterfeiting of integrated circuits (ICs), in particular IC recycling, has become a serious issue in recent years. Recycled ICs are those harvested from old systems and resold in the supply chain as new. Such ICs exhibit lower performance and shorter lifetime and, as a result, pose threats to the security and reliability of electronic systems. In this paper, we propose a recycled IC detection framework called static random-access memory (SRAM)-based countermeasure against IC recycling (SCARe) to detect the aging of SRAM cells. Our framework can be applied to both standalone SRAM chips and system on chips with embedded SRAM. For each SRAM under detection, statistical analysis is conducted to differentiate the recycled and new ICs. To mimic the practical aging scenario, 16 commodity SRAM chips from three different manufacturers and different technology nodes (e.g., 90, 110, and 130 nm) are stressed under high-temperature and supply-voltage conditions for different periods of time. The experimental results from new and aged SRAM chips, which represents recycled ICs, demonstrate that our proposed technology can achieve extremely high-detection success rate (no lower than 96.5%). The minimal in-field usage, which can be detected by SCARe, is 7 h.

Methods for Estimating the Convergence of Inter-Chip Min-Entropy of SRAM PUFs

For cryptographic applications based on physical unclonable functions (PUFs), it is very important to estimate the entropy of PUF responses accurately. The upper bound of the entropy estimated by compression algorithms, such as context-tree weighting, is too loose, while the lower bound estimated by the min-entropy calculation is too conservative, especially when the sample size is small. The actual min-entropy is between these bounds but is difficult to estimate accurately. In this paper, two models are proposed to estimate the convergence of the inter-chip min-entropy of static random-access memory (SRAM) PUFs. The basic idea is to find the relation between the expectation of the estimation result and the tested sample size, and then predict the convergence of the min-entropy. Furthermore, an improved Von Neumann extractor is used to increase the entropy per bit while retaining as many responses as possible for error correction. The experimental results demonstrate that the prediction error of the proposed estimation methods is less than 0.01/bit for the tested SRAM chips, and the improved Von Neumann extractor can reduce the number of required responses by approximately 11/16, the amount of helper data by 2/3, and the number of masks by 3/8 compared with the original method.

Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network

For Internet of Things (IoT) edge devices, it is very attractive to have the local sensemaking capability instead of sending all the data back to the cloud for information processing. For image pattern recognition, neuro-inspired machine learning algorithms have demonstrated enormous powerfulness. To effectively implement learning algorithms on-chip for IoT edge devices, on-chip synaptic memory architectures have been proposed to implement the key operations such as weighted-sum or matrix-vector multiplication. In this paper, we proposed a low-power design of static random access memory (SRAM) synaptic array for implementing a low-precision ternary neural network. We experimentally demonstrated that the supply voltage (VDD) of the SRAM array could be aggressively reduced to a level, where the SRAM cell is susceptible to bit failures. The testing results from 65-nm SRAM chips indicate that VDD could be reduced from the nominal 1–0.55 V (or 0.5 V) with a bit error rate ~0.23% (or ~1.56%), which only introduced ~0.08% (or ~1.68%) degradation in the classification accuracy. As a result, the power consumption could be reduced by more than $8\times $ (or $10\times $ ).

Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells

Physical unclonable functions (PUFs) are circuits that produce outputs determined by random physical variations from fabrication. The PUF studied in this paper utilizes the variation sensitivity of static random access memory (SRAM) data retention voltage (DRV), the minimum voltage at which each cell can retain state. Prior work shows that DRV can uniquely identify circuit instances with 28% greater success than SRAM power-up states that are used in PUFs [1]. However, DRV is highly sensitive to temperature, and until now this makes it unreliable and unsuitable for use in a PUF. In this paper, we enable DRV PUFs by proposing a DRV-based hash function that is insensitive to temperature. The new hash function, denoted DRV-based hashing (DH), is reliable across temperatures because it utilizes the temperature-insensitive ordering of DRVs across cells, instead of using the DRVs in absolute terms. To evaluate the security and performance of the DRV PUF, we use DRV measurements from commercially available SRAM chips, and use data from a novel DRV prediction algorithm. The prediction algorithm uses machine learning for fast and accurate simulation-free estimation of any cell's DRV, and the prediction error in comparison to circuit simulation has a standard deviation of 0.35 mV. We demonstrate the DRV PUF using two applications-secret key generation and identification. In secret key generation, we introduce a new circuit-level reliability knob as an alternative to error correcting codes. In the identification application, our approach is compared to prior work and shown to result in a smaller false-positive identification rate for any desired true-positive identification rate.

소프트 에러율에 대한 박막 트랜지스터형 정적 RAM의 신뢰성

We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from . As the polysilicon-2 thickness increased up to , the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer

Monte Carlo simulation of the SRAM single event upset

The process of deposited energy in sensitive volumes in a static random access memory (SRAM) chip induced by 10—20MeV neutrons is simulated using the Monte Carlo method. In the simulation, the physical parameters related to the single event upset (SEU) of the SRAM chip are calculated. The results provide detailed statistical data for the SEU process induced by 10—20MeV incident neutrons, and reference information for the deface reinforcement of the SRAM chip.

Development of an Abstract Model for a Non-volatile Static Random Access Memory

The capability to protect against power fluctuations, which eventually prevents the corruption of the memory contents makes non-volatile static random access memory a very good choice for use in highly reliability applications. These random access memories are protected against data writing in addition to preserving the desired contents. Energy source and control circuitries are embedded into it for achieving the same. The control circuitry constantly monitors supply voltage level, inhibits data corruption, and switches on the energy source once it falls beyond a threshold level. In this paper, development of an abstract model for such a non-volatile static random access memory chip has been presented. Test sequences based on this model have been generated for this memory chip. These test sequences have been implemented in VLSI tester and exercised on the chips.

Multiscale Modeling of Thin-Film Deposition: Applications to Si Device Processing

Metallization is the back end of the integrated-circuit (IC) fabrication process where the transistor interconnections are formed. Figure 1 shows the metallized part of a static random-access memory chip. Metal lines for electrical connections (Al and Cu) in Si devices are deposited as blanket films and then etched or polished away to define the conducting lines.

Investigating material and functional properties of static random access memories using cantilevered glass multiple-wire force-sensing thermal probes

A double-wire cantilevered glass probe has been produced for scanned probe microthermal, resistivity, and topographic measurements. The structure has many potentially unique properties for scanned probe microscopy and other nanotechnological measurements. In this letter, a double Pt wire probe was fused at the tip and applied to thermal resistive measurements. The probe operation is based on the linear dependence of Pt resistance on temperature. Most microscopic structures are composed of a variety of materials. In the present study, the features of a static random access memory chip are investigated. Such memory chips are composed of materials such as dielectrics, metals, and semiconductors. We demonstrate that these samples, which are prepared using a chemical–mechanical polishing procedure and have essentially no surface topography, can be inspected using the thermal conductivity, resistivity, and topographic sensitivity of these probes.

Failure analysis of integrated circuits beyond the diffraction limit: contact mode near-field scanning optical microscopy with integrated resistance, capacitance, and UV confocal imaging

Superresolution reflection near-field scanning optical microscopy (NSOM) of ultra-large-scale integrated circuits (ULSI) that have been subjected to chemical mechanical polishing (CMP) are presented. These NSOM images are rich in contrast, unlike simultaneously recorded atomic force microscopy (AFM) images. The NSOM data are compared to reflection confocal far-field optical microscopy using ultraviolet radiation with a wavelength of 248 nm, which has a resolution close to 0.2 /spl mu/m. Even though there is a significant thickness of oxide between the tip and the layer being imaged the data recorded with visible light clearly exhibits higher resolution than those ultraviolet confocal images that have undergone computer deconvolution. The AFM images exhibit no topography representing circuit features because the CMP operation that these static random access memory chips (SRAMs) have been subjected to produces flat topographic free surfaces. In terms of NSOM imaging, this is most interesting since the contribution of topography is totally removed and index of refraction variations are the only source for these rich NSOM images. Clearly, these NSOM images with cantilevered NSOM elements are free from topographic artifacts. Furthermore, simultaneous imaging of NSOM, normal force topography, and functional electrical characteristics such as capacitance and resistance are presented on these SRAMs. This demonstrates the ability of NSOM to act as a tool that provocatively integrates the best of far-field, optical imaging on the one hand with the most advanced scanned probe electrical imaging of circuit function on the other.

Performance analysis of multilayer interconnections for megabit static random access memory chip

Performance analysis of multilayer interconnections for megabit static random access memory chip

Fabrication of high performance 512K static-random access memories in 0.25 μm complementary metal–oxide semiconductor technology using x-ray lithography

Functional 512K static random access memory (SRAM) devices containing more than 3.6 million transistors have been successfully fabricated in a 0.25 μm complementary metal–oxide semiconductor technology using compact storage ring x-ray lithography. In this demonstration a comparison of critical dimension control was made between x-ray and optical (i-line and excimer laser) lithography by fabricating SRAM devices using both lithographic techniques. For the x-ray fabricated devices the channel length, a key device performance parameter, was controlled to within 0.036 μm (3σ), demonstrating the excellent process robustness, and dimensional control available from x-ray lithography. These SRAMs had excellent electrical characteristics, including cycle times of 1.8 ns and access times of 3.7 ns. The ability of the existing x-ray lithography infrastructure to produce a fully functional (‘‘perfect’’) chip has been demonstrated in a companion device fabrication program. A 512K SRAM chip of a slightly different design, with 0.35 μm minimum channel length, was fabricated with 100% bit yield using x-ray lithography. This article describes these device demonstrations, including the observed advantages of x-ray lithography, as well as the status of IBM’s x-ray lithography program and associated infrastructure.

Performance analysis of multilayer interconnections for megabit static random access memory chip

Interconnections problems in the megabit static random access memory (SRAM) chip are studied. A multilayer interconnect capacitance model is developed, and effects of interconnection on SRAM device performance parameters, such as propagation delay, speed, power consumption, and noise characteristics, are analyzed. A case study of 1-Mb SRAM chip interconnection is discussed. A multilayer interconnect approach is proposed to overcome on-chip interconnection difficulties. By implementing a double-layer interconnect approach, the wire length and chip size were reduced to 69% and 58%, respectively. Maximum access time of 30.8 ns with 1 W at 100 degrees C and wafer yield as high as 10% was achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Proton-sensitive custom SRAM detector

Because of the recently discovered importance of protons to the upset of spaceborne electronics, a custom 4-kB SRAM (static random-access memory) chip was tested with protons. The SRAM was developed to determine the single-event-upset hardness of CMOS latches using alpha particle measurements, by adjusting an offset voltage that reduces the charge required to upset a cell. The authors describe a calibration procedure for the SRAM detector. Source spectra were acquired with this chip by measuring the number of upset cells versus offset voltage. The SPICE assisted calibration utilizing 56 fC/V and the proton data identified a 4.32-pm silicon equivalent overlayer and a 6.64+or-0.31 mu m effective charge collection depth for protons and a 6.33- mu m collection depth for alpha particles. These collection depths can be used to predict the SRAM detector response to proton-produced ionization in space. The SRAM collects all of the charge from silicon recoils produced by Rutherford scattering; this charge is collected from very deep in the SRAM substrate. >

A static random-access memory with normally-off-type Schottky barrier FET's

A large-scale integrated memory with lower power consumption and high operating speed has been developed and evaluated. A fully decoded 256-b static random-access memory chip was fabricated by using the Enhancement-type Schottky Barrier gate FET's, having a threshold voltage of 0.1 V, obtained by ion-implantation. The memory chip was successfully operated with an access time of less than 150 ns, and with active power consumption of 15 mW/chip. A single power supply of -1.3 V and current mode logic input levels are additional features of the memory chip.