Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor

Abstract

The robustness of Static random access memory (SRAM) Physical unclonable functions (PUFs) is threatened by the state change of the power-up value (R) at different temperatures. The voltage ramp-up time Tramp is one of the factors that can affect the stability of R. Some studies have been performed on the Tramp of commercial SRAM chips at the microsecond (μs) level. In this paper, a robust and low cost SRAM PUF using a p-channel metal oxide semiconductor (PMOS) as a power switch to enhance the stability of R is proposed. Tramp is as fast as 11 V/ns. The proposed SRAM PUF has a linear shift register extractor, with an extraction rate as high as 7/18 and no helper data in contrast to traditional von Neumann extractor. This chip has been fabricated using 0.11 μm ultra-low-leakage technology. The experiment results show that R becomes stable at [-40 °C, 85 °C], and a simple lightweight error correcting codes (ECC) can be used in SRAM PUF.