Static Random Access Memory Cell Research Articles

Schmitt Trigger 12T1M Non-volatile SRAM cell with improved process variation tolerance

This paper presents a Schmitt Trigger (ST) based 12T1M non-volatile static random-access memory (nvSRAM) cell which significantly provides tolerance against process variations. The memristor M1 is connected between internal node Q and bitline RBL through read pass transistor. The impact of process variation is studied on margin and delay performances of proposed and existing read decoupled (RD) nvSRAM cells. The proposed cell achieves 1.62X, 1.17X and 1.33X higher write, read and hold margins, respectively, in comparison to existing RD nvSRAM cells. Furthermore, the maximum reduction in write, read and hold failure probabilities by 105×, 104× and 104×, respectively, is observed for proposed cell. The overall Vmin of proposed cell is found as 425 mV which is minimum among the existing RD counterparts. In addition, there is significant reduction in leakage power consumption and write/read delay deviation for the proposed cell. The store/restore performance of the proposed cell is same as most of the considered cells. All the comparison are made using 32 nm CMOS PTM model and at Vdd = 0.6 V. The effect of supply voltage variation is also studied on the performance of proposed and existing RD nvSRAM cells for the sake of completeness.

Area-efficient radiation-hardened 6 T SOI SRAM cell design using TDBC Transistors

Single event upset (SEU) is a critical issue for the static random access memory (SRAM) exposed to irradiated environments. In this paper, an area-efficient 6 T SRAM cell design based on partially depleted silicon-on-insulator (PDSOI) technology is proposed to improve the ability to resist SEU using tunnel-diode body-contact (TDBC) transistors. The proposed cell and 6 T floating body (FB) SOI SRAM cell are fabricated using 130 nm PDSOI technology for comparison purposes. Pulsed laser experiments show that, at the nominal supply voltage of 1.2 V, the energy threshold of the proposed cell increases by 25.2 % compared to the 6 T FB SOI cell with a similar area. The energy threshold of the traditional T-gate body-contact (TB) cell is also compared with that of the proposed cell.

A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

Carbon nanotube field effect transistor (CNTFET) is swiftly becoming an alternative to conventional CMOS transistors due to superior transport properties, improved current handling characteristics, and better gate control. This work presents a new Carbon nanotube field effect transistor (CNTFET) based low power, stable static random access memory (SRAM) cell design with reduced write delay. The proposed eight-transistor (8T) CNTFET-based SRAM cell improves read/write static noise margin by 1.98×/1.25×, respectively, at 0.3 V compared to conventional 6T SRAM that uses similar CNTFET parameters. The write access time and leakage power of the proposed cell are improved by 1.90× and 2.14×, respectively, compared to the conventional 6T design. The proposed design parameters are also compared with two already presented 8T SRAM cells. The simulation is performed with the Cadence Virtuoso using the Stanford University 32 nm CNTFET Verilog model.

Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design

For low voltage CMOS static random access memory (SRAM) cells, the leakage current on bit-lines will slow down the reading operation and even lead to error reading. Herein we report a 4B4C circuit composed of 8T SRAM arrays, four bit-lines and four coupling capacitors to track and compensate the bit-line leakage current (BLLC). The assistant bit-lines are used to control the connection of capacitors. The coupling capacitors are used to compensate voltage losses caused by the BLLC, and improve the maximum tolerable current from primary bit-line. The timing diagram and output waveforms verify the compensatory effects of coupling capacitors. The 4B4C circuit shows fast reading operation and increases the maximum tolerable leakage current to 17.8 times compared with conventional circuit at FS process corner. The 4B4C circuit can keep 100% correct reading till 200 μA from Monte Carlo simulations. The 4B4C circuit enhances SRAM reading reliability and shows huge potential in very-large scale memory arrays.

Performance evaluation of SRAM design using different field effect transistors

SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it. Unlike Dynamic RAM, Static RAM uses a flip-flop circuit to store each data bit, whereas Dynamic RAM uses a capacitor to store the data bit. But capacitor has tendency of losing charge which requires periodic refreshment. Thus SRAM perform better and have more stability than DRAM especially in idle state. In this work, we analysed the performance of the SRAM cell which are built with different field effect transistors and calculated the Write and Read delays, PDP (Power Delay Product) and Static Noise Margin (SNM) for all types of transistors. SRAM cell which is based on the CNT technology with optimized parameters of CNT density, CNT diameter and CNTFET flat band voltage has the better performance and stability compared with other device technologies. Optimized CNTFET SRAM cell compared with the MOSFET based SRAM the write and read delays are improved by 85.8% and 94.3% respectively. All the simulations have been carried out using HSPICE tool for 32nm technology node.

Influences of well contact on multiple-cell upsets in 28 nm SRAM

In order to study the effects of the feature size reduction and well contact placement on the characterization of topology patterns and the charge collection mechanism of device heavy ion single event multiple upset on a nanometer scale, the heavy ion single event effect experiment on the domestic 28 nm static random-access memory (SRAM) is carried out on the experimental platform of HI-13 heavy ion accelerator in Beijing. Based on the mapping relationship between the logical address and physical address of the device, the experimental data are processed, and the 28 nm SRAM heavy ion single event upset cross section curves, multiple upset percentage, and multiple upset topology patterns are obtained. The results are compared with those of heavy ion single event effect experiments in 65 nm SRAM, showing that under the influences of factors such as feature size reduction and lower operating voltage, the heavy ion single event upset threshold and the bit upset saturation cross section of 28 nm SRAM decrease significantly. In the direction perpendicular to the well, owing to the reduced 28 nm SRAM feature size, even if the single nucleon energy of the incident high LET (linear energy transfer) heavy ion is low, its deposited charge is sufficient to affect the three SRAM cells across the well direction due to the combined effect of ion track coverage, well potential modulation caused by the parasitic bipolar amplification effect and carrier diffusion, resulting in the fact that the 28 nm SRAM topology pattern has a shape of <i>n</i> rows × 3 columns, which poses new challenges and requirements for the anti-radiation hardened technology with scrubbing and EDAC (error detection and correction). Owing to the global well contact deployment, the charge deposited by the incident ions in the well far away from the well contact is difficult to discharge quickly, and the parasitic bipolar amplification effect lasts longer. The charge sharing competition between two p-channel metal oxide semiconductor in SRAM cell causes the single event upset recovery, which is the fundamental reason why the discontinuity of multiple upset topology pattern appears in 28 nm SRAM. This study provides a new anti-radiation hardened idea for suppressing the single event upset by using the parasitic bipolar amplification in the future.

A Read-Decoupled Error-Tolerant 10T SRAM Cell in 32nm CMOS Technology

Stability of static random access memory (SRAM) cells has become a growing concern in the nanometer regime. In order to address this issue, this paper proposes a read-decoupled 10 transistor (10T) SRAM cell. The decoupled-read feature of the proposed 10T SRAM cell protects it from the read-disturbance problem, thereby achieving enhanced read stability. Additionally, the bit interleaving capability of the cell provides immunity to soft errors. The simulation is performed on TSPICE software using a 32 nm CMOS predictive technology model. The obtained results reveal that the read static noise margin - at 400 mV - of the proposed design is 4.77x and 1.38x larger compared to that of a 6T cell and the Schmitt-trigger based 10T cell, respectively. Moreover, the write power consumption in the proposed design is found to be 1.86x lesser than that of a 6T cell. Furthermore, the proposed circuit exhibits 3.47x lesser static power consumption compared to a 6T cell.

Performance Analysis Of SRAM and Dram in Low Power Application

All electronic systems must function quickly in the current environment, and 80 percent of electronic chips have memory components. SRAM (Static Random Access Memory) has thus become a major key component in many VLSI Chips in order to reduce the size of the memory chips, to increase the speed, to reduce leakage current, and to increase the power efficiency. Due to its high storage density and quick access time, it has also become a popular data storage device. SRAM has been given priority in the research community due to the recent sharp development in low power and low voltage memory devices. In this study, the design and performance of SRAM and DRAM cells were analyzed. This paper outlines the development and application of modified 6T SRAM cell with increased power efficiency.

DESIGN OF A 6T SRAM CELL WITH MINIMAL POWER USING CADENCE VIRTUOSO

It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three source biasing techniques are used. At 45 nanometer and 90 nm technology nodes, the three techniques are NMOS diode clamping, PMOS diode clamping, and NMOS-PMOS diode clamping. The implementation of a 6T SRAM cell using the Multiple Threshold CMOS (MTCMOS) technique at 45nm technology is also emphasised in this article. Using the cadence virtuoso tool, the simulation is completed and different power dissipations are examined for 45 nm and 90 nm technologies, respectively, at supply voltages of 0.45 V and 0.9 V. Comparing PMOS clamping to the other two suggested techniques, an average power reduction of 82.19% was observed.

Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.

Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAM

We present a low-leakage graphene nano-ribbon transistors (GNRFETs)-based static random access memory (SRAM) cell in 16nm technology that operates near the sub-threshold region in this study. In comparison to conventional Si-CMOS technology, the proposed cell improves read stability and writeability by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.67\mathbf {\times }$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.14\mathbf {\times }$ </tex-math></inline-formula> , respectively. The proposed cell considerably outperforms the existing 9T SRAMs cell in terms of power consumption, latency, read stability, and write-ability, according to the HSPICE simulation. In addition, at the low supply voltage of 325mV, the multi-threshold approach and transistor optimizations are used to improve the read static noise margin (RSNM). The proposed cell’s overall power consumption is lowered by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4161\mathbf {\times }$ </tex-math></inline-formula> when compared to a conventional 6T SRAM cell while using the multi-threshold approach in the write port. Device optimization and the multi-threshold approach, which enhances read and write performance, can considerably minimize read and write delays.

Performance Analysis of 6T SRAM and ONOFIC Cells

Background: As the technology node scales down to a deep sub-micron regime, the design of static random-access memory (SRAM) cell becomes a critical issue because of increased leakage current components. These leakage current components prevent the designing of a low-power processor as a large portion of the processor power is consumed by the memory part. Objective: In this paper, an SRAM cell is designed based on the ON/OFF logic (ONOFIC) approach. Static noise margin (SNM) of the cell for the different states are calculated and evaluated by using the butterfly as well as noise (N) curves with the help of Cadence tools at 45 nm technology node. Methods: ONOFIC approach reduces the leakage current components, which makes a low power memory cell. A performance comparison is made between the conventional six-transistor (6T) SRAM cell and memory cell using the ONOFIC approach. Results: Low value of power delay product (PDP) is the outcome of the ONOFIC approach as compared to conventional cells. ONOFIC approach decreases PDP by 99.99% in case of hold state. Conclusions: ONOFIC approach improves the different performance metrics for the different states of the SRAM cell.

Low leakage, differential read scheme CNTFET based 9T SRAM cells for Low Power applications

ABSTRACT Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs.

Novel radiation-hardened SRAM for immune soft-error in space-radiation environments

As the feature size of transistors scaling down, the integration density of memory circuits such as Static random access memory (SRAM) cells increases, and they are more sensitive to Single event effect (SEE). The Single event multiple node upset (SEMNUs) caused by charge sharing effect is becoming a major concern in memory circuit design. In this paper, a new radiation-hardened SRAM cell (NRHC-14T) is proposed on the basis of considering the radiation-hardened and the operating performance of the basic circuit. The circuit uses polarity hardening technology to reduce the number of sensitive nodes, and can recover from Dual-node upset (DNU) on the basis of all single-node upset (SNU) recovery. Compared to other radiation-hardened cells, NRHC-14T cell than We-Quatro, DICE, SAR14T, RSP14T, RHPD-12T, QUCCE12T, and SEA14T increased by 60.12 %, 9.22 %, 21.39 %, 84.34 %, 17.92 %, 100.58 %, and 129.48 % of the writing speed, and saved by 34.28 %, 57.14 %, 22.85 %, 11.43 %, 68.57 %, 34.28 %, and 79.99 % of the power consumption, respectively. In addition, NRHC-14T has better stability, the highest Critical charge (Qcrit) and the best overall performance. The cell proposed in this paper can be well used to aerospace electronic devices and work stably in space radiation environment by virtue of its excellent radiation-hardened ability and good overall performance.

Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

This paper comparatively analyzes the static random-access memory (SRAM) cell designs for fault tolerance. Since SRAM cells are sensitive to radiation-induced single event upsets, various circuit-level approaches have been applied. Compared to the conventional SRAM cell circuits, one possibility is adding redundant storage nodes by means of additional transistors. The strength and weakness of the SRAM cells in terms of various performance aspects—speed, area, power, stability, fault tolerance, etc.—according to the design approaches are compared analytically and discussed. The discussion concludes that, in the future, it is paramount to develop an SRAM cell design with a mitigated trade-off between read/write performance and SEU tolerance.

Design of a stable single sided 11T static random access memory cell with improved critical charge

AbstractRadiation‐induced soft errors are becoming a key challenge in satellite‐based communication. The worst‐hit component of such devices is static random‐access memory bit‐cells, owing to their high density, large area, and low‐operating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge‐boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft‐error‐immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13×/1.38×/0.90×/1.04×/1.03× improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31×/1.17×/1.31×/1.41×/1.01× compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97×/0.98×/1.91×/1.24×/1× when equated to 6T/PP10T/AS8T/Quatro10T/LC10T cell. Improved Inter‐cell and Intra‐cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability.

Cross-Coupled Gated Tunneling Diodes With Unprecedented PVCRs Enabling Compact SRAM Design—Part II: SRAM Circuit

In Part I of this article, we present a novel device, i.e., a cross-coupled gated tunneling diode (XTD), which exhibits negative differential resistance (NDR) with peak-to-valley current ratios (PVCRs) exceeding 105. In this part of this article, based on the XTD, we introduce a compact static random access memory (SRAM) cell using a one-transistor and two-XTD (1T-2X) design. The layout of the SRAM cell as well as a detailed analysis of the cell behavior and SRAM array performance are presented. In particular, our simulation results show that the 1T-2X SRAM cell can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$70\times $ </tex-math></inline-formula> improvement in standby power with ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> area reduction compared to standard CMOS SRAM.

A New Design Paradigm for Auto-Nonvolatile Ternary SRAMs Using Ferroelectric CNTFETs: From Device to Array Architecture

Preserving the data stored in a static random access memory (SRAM) during power gating or a sudden power outage is a necessary but costly need. This work proposes an ultraefficient auto-nonvolatile ternary SRAM (ATSRAM) cell using ferroelectric carbon nanotube field-effect transistors (Fe-CNTFETs). By harnessing the unique features in Fe-CNTFETs, the proposed ATSRAM utilizes only 12 transistors. The proposed design can automatically perform backup and restore operations without additional resources and nonvolatile elements during a power outage. This unique specification eliminates the redundancies usually required to provide nonvolatility. The utilized hysteretic cross-coupled two-transistor standard ternary inverters (STIs) provide a superior static noise margin (SNM) beyond the binary SRAMs and the ideal noise margin limitation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula> /4). The proposed ATSRAM array structure benefits from a row-shared supply disconnector to mitigate the static current drawn from the power supply during data retention. Our results demonstrate that the proposed ATSRAM indicates, on average, 40% improvement in transistor count, 2.8 times higher SNMs, 27% reduction in total power consumption, and 41% (66%) improvement in the read (write) energy compared with the state-of-the-art volatile ternary SRAMs. In a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${32} \times {32}$ </tex-math></inline-formula> ternary array configuration, 94% (98%) improvement in the read (write) energy is obtained compared with the other counterparts. Our design methodology provides a new paradigm for designing ultraefficient and ultracompact nonvolatile multivalued logic (MVL) memories using ferroelectric-based FETs.

Cross-Coupled Gated Tunneling Diodes With Unprecedented PVCRs Enabling Compact SRAM Design—Part I: Device Concept

Tunnel diodes (TDs) and resonant tunneling diodes (RTDs) with negative differential resistance (NDR) have attracted interest in implementing high-density, low-power circuits, such as static random access memory (SRAM). However, the low peak-to-valley current ratios (PVCRs) in these devices cause high static leakage currents, leading to poor performance in the circuits and limiting their application. This article presents a novel device, i.e., a cross-coupled gated tunneling diode (XTD), that exhibits NDR with PVCRs exceeding <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{5}}$ </tex-math></inline-formula> . The device design is validated by TCAD simulation as well as an experimental demonstration. In contrast to conventional TDs, which operate in the forward bias direction, the XTD operates in the reverse bias direction, thus suppressing thermionic emission and trap-assisted tunneling (TAT) currents, which together allow for the large PVCR. In Part II of this article, we continue to discuss compact, low-power SRAM cells based on the XTD.

An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit

Standard-cell-based memory (SCM) circuits with fully digital signals are attractive for power-/energy-constrained edge devices due to the strong voltage scaling capability, fast design iteration, and flexibility in integration. In this article, a 13-transistor (13T) static-random access memory (SRAM) circuit with ultra-wide range voltage scaling capability is proposed for ultra-low-power applications. By adopting the concept of SCM, the 13T SRAM cell is custom-designed, while providing fully digital inputs and outputs. Without any analog circuitry, the 13T memory array is fully synthesizable and compatible with the commercial semi-custom design flow. A specialized circuitry is employed in the 13T SRAM cell to enable cell-level bit-interleaving. An 8-kb 13T SRAM bank is fabricated in the UMC 55-nm low power CMOS technology, achieving an area density of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5 \mu \text{m}$ </tex-math></inline-formula> 2/bit. The minimum operational voltage for the 13T SRAM circuit is 324 mV, while the data retention voltage is down to 279 mV. The 13T SRAM circuit achieves the minimum energy point at 0.4 V for both the read (32.8 fJ/bit) and write (54.1 fJ/bit) operations, providing a good opportunity to perform voltage scaling together with logic blocks when embedded in the same power domain.