Static Noise Margin Research Articles

Reliability improved dual driven feedback 10T SRAM bit cell

This paper presents a dual driven feedback 10T (DDFB10T) static random-access memory (SRAM) bit cell with good read and write stability and that is free from half select issue. This DDFB10T cell working at VDD = 0.9 V achieves 1.5× higher static voltage noise margin (SVNM), and 0.48× lesser write trip voltage (WTV) than 6T SRAM cell. Monte Carlo simulation employing local and global variation using Cadence Virtuoso tool with 45 nm technology proves that the proposed bit cell is highly immune against process, voltage, and temperature (PVT) variations. The proposed DDFB10T bit cell exhibits lesser SVNM variability when it is normalized to that of 6T SRAM bit cell. The proposed DDFB10T cell is designed with the capability to provide a bit interleaved architecture for reducing half select issues.

Single-Ended 8T SRAM cell with high SNM and low power/energy consumption

ABSTRACT This paper introduces an 8T single-ended SRAM cell to improve stability and decrease energy consumption. It cuts the pull-down path to the storage node written ‘1’, enhancing the write ability. It uses an isolated read path to enhance the read stability with low power and energy consumption. At a supply voltage of 0.5 V, the read static noise margin, write margin, read energy, and write energy of the proposed cell are superior by 320%, 233%, 12%, and 26%, respectively, compared to the conventional 6T. We performed 5,000 Monte Carlo simulations in the 32 nm technology to evaluate read yields. The results show that our cell has 6.9x more yields than the conventional 6T SRAM cell. Therefore, the proposed cell can be a good option for high stability and low power/energy applications.

One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

AbstractThis paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms.

Improved Read/Write Stability-Based Level Shift 5T Ternary SRAM Cell Design Using Enhanced Gate Diffusion Input BWGCNTFET

Nowadays, CNTFET introduced the complexity of SRAM design along with the stability. To overcome these complexities, an enhanced Gate Diffusion Input technique-based Ballistic wrap gate CNTFET (EGDI-BWGCNTFET) technology with ternary static random-access memory (T-SRAM) is proposed in this paper. The aim of the proposed technique is “to give higher stability with less stagnant power consumption, voltage drop and store appropriate read/write value of the SRAM cells”. Here, level shift 5T ternary SRAM cell design using Enhanced Gate Diffusion Input Ballistic wrap gate CNTFET (level shift EGDI-BWGCNTFET 5T-ternary SRAM) is proposed for improving read and write stability. It uses two cross-coupled EGDI-BWGCNTFET ternary inverter, which is used for data storage elements along with one access transistor which is connected with bit line (BL) and word line (WL) with minimum supply voltage resulting in leakage current that is decreased. By this, proposed method reduces delay in the write cycles and read cycles. It provides good read static noise margin (RSNM) and controls precharge voltage. The proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM is done in HSPICE platform. The performance of the proposed level shift EGDI-BWGCNTFET 5T-ternary SRAM design is measured in terms of lower Read Delay 23.25%, 22.94%, 18.38%, 23.97%, lower Write Delay 33.92%, 28.94%, 42.83%, 31.98% compared with the existing methods, such as 8T CNTFET-Ternary SRAM, 24T CNTFET-2Ternary SRAM, 18T CNTFET-Ternary SRAM and 17T CNTFET-Ternary SRAM, respectively.

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

Many researchers are trying to create a low power, high stability, and high-speed static random access memory (SRAM) cell. This paper introduces an SRAM cell consisting of 12 transistors (12 T) developed by carbon nanotube field-effect transistor (CNTFET) to support such an endeavor and be a milestone in creating a better SRAM cell. The proposed 12 T CNTFET SRAM cell is a modified Schmitt-trigger (ST)-based SRAM cell design. The ST-based SRAM cell feedback-cutting and single-ended read decupled techniques are introduced to improve the SRAM cell’s static noise margin (SNM) and access time. The presence of stacked N-CNTFETs reduces the proposed cell’s power consumption. In addition to conventional 6 T [9] and 8 T [10] SRAM cells, it has been compared with some of the existing SRAM cells such as 12 T SRAM [11], 12 T SRAM [12], 12 T SRAM [13] and 12 T SRAM [14], for calculating the relative performance of the proposed 12 T CNTFET SRAM cell design in terms of fundamental design metrics. The simulation results at 0.9 V show that compared to the afromentioned bit cells, the proposed design accomplishes low power consumption while writing, reading, and holding modes of operation. It has a high SNM during all the operations. The proposed cell has the least read access time. The power, SNM, and access time performance of the bit cells are evaluated for the variation of CNTFET parameters and reported in this article. The proposed cell is also implemented using MOSFET, and the performance of MOSFET and CNTFET is compared. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model.

Analysis of back-gate bias impact on 22 nm FDSOI SRAM cell

The back-gate terminal biasing has been used to improve the SRAM cells’ performance. In this paper, the impact of back-gate bias on the performance of 22 nm FDSOI SRAM 6T cell is analyzed. The cell is fabricated in the regular well and two back-gate terminals are connected to Pwell and Nwell, respectively. The influences of back-gate bias on the cell are studied by the variations of the metrics of leakage current, read current, static noise margin (SNM) and N-curve under the three back-gate bias combinations. Through measurements and HSPICE simulations, the mechanism of the variations of the cell metrics caused by the changes of the back-gate bias is explained by the shift of electrical characteristics of transistors inside the cell.

Design and investigation of stability‐ and power‐improved 11T SRAM cell for low‐power devices

AbstractThe modern system‐on‐chips require stable and low‐power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability‐ and power‐improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross‐coupled structure of a conventional inverter with a N‐type stacked transistor and a Schmitt‐trigger (ST) with a double channel‐length pull‐up network. This coupled with a separate read path enhances the read static noise margin (RSNM). Moreover, a feedback‐cutting N‐type transistor is placed inside the cell core to improve the write static noise margin (WSNM)/write margin (WM). Though the presence of stacked transistors in access paths increases read delay (TRA)/write delay (TWA), it reduces leakage. This metric further minimizes with the aid of a stacked structure of latch core and double channel‐length of pull‐up transistor in the ST inverter. The moderate read/write frequency and single‐ended structure of the suggested cell result in low dynamic power. Simulated results by using 16‐nm CMOS at VDD = 0.7 V show that the proposed cell has the second‐best RSNM/WSNM, which is 4.65/1.44 times higher than that of the fully differential 8T (FD8T) cell, as the basic cell. Moreover, it reduces leakage power by at least 2.01 times and consumes moderate read/write power, nearly 1.44/1.81 times lower than that of FD8T cell, at the cost of 1.61 times area overhead. The proposed cell can eliminate read/write‐half‐select‐disturbance issues to support bit‐interleaving architecture to increase soft error immunity.

Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate

The failure probabilities of industrial SRAM cells fall below the ppm (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−6</sup> ) range, disqualifying the computational-intensive Monte-Carlo simulations for efficient robustness assessment. Starting from a novel two-dimensional threshold voltage imbalance representation, we propose a new methodology for fast and accurate prediction of the subthreshold SRAM hold stability failure rate. The probability is derived in a closed form which involves the transistor threshold-voltage standard deviations and only requires the two quick DC extractions of the worst- and best-case static noise margins. We validate our approach on a Six-Transistor (6T) bitcell in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology. Our method turns out to be especially insightful for comparative and sensitivity analyses, for instance to study the effect of supply voltage downscaling or temperature variations. Finally, we show that the achieved accuracy and the capability of estimating extremely low failure probabilities (down to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−9</sup> ), combined with the important gain in simulation and post-processing cost, makes our methodology attractive compared to other recent modelling works.

Robust transmission gate-based 10T subthreshold SRAM for internet-of-things applications

This paper presents a transmission-gate-based 10T (TG10T) subthreshold SRAM cell for internet of things applications. To estimate its relative strength, it is compared with six-transistor (6T), transmission gate (TG)-based 8T (TG8T), and fully differential 8T (FD8T) cells subjected to severe process variations. The simulation results are carried out using HSPICE software and a 16 nm CMOS technology node. The TG10T cell uses a differential scheme to enhance the sense margin, two TGs instead of two NMOS access transistors to enhance write-ability, and two extra buffer transistors to improve read stability. The proposed TG10T cell minimizes leakage power dissipation by means of a greater number of PMOS devices. The proposed cell shows at least a 1.67X lower read delay (T RA) and a 1.13X higher read static noise margin. In addition, it offers a 1.22X and 1.52X lower write delay (T WA), and a 1.36X and 1.40X higher write static noise margin (WSNM) than that of 6T and FD8T, respectively. The TG10T cell consumes 2.06X/1.28X lower dynamic/leakage power compared to the 6T cell. For all these improvements, it incurs a penalty of 1.24X T WA, 1.48X WSNM, and 1.12Xdynamic power when compared with the TG8T cell, at V DD = 0.36 V. However, when subjected to severe process variations, the proposed TG10T cell shows high reliability. Moreover, a 2 kb SRAM memory using the proposed TG10T cell along with peripheral circuitries is implemented to evaluate the proposed cell’s performance in an array level.

Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies

The growing markets for low-power electronic devices energized by battery have created the need for smaller power-efficient chips to prevent frequent charging of the source. Nowadays the market capitalization of low-power appliances is expected to grow from USD 4.9 billion by 2022 to USD 7.9 billion by 2027 as per global forecast to 2027 published by markets. The main factor leading to growth of low power electronics market includes demand of energy saving components, miniaturization, and entry of IoT (internet of things) devices. In addition, increased investment by automotive OEM (Original Equipment Manufacturer) and governments to promote the adoption of electric vehicles is expected to create more market opportunities. In this digital era, memory components play a major role in power consumption and this incites the research interest these days. CMOS (Complementary Metal Oxide Semiconductor) technology is growing rapidly towards greater integration into a single chip, resulting to a decrease in chip sizes using less space. Speed and stability demand is also growing up. Combined chip density increases as downtime technology continues. Stability and reliability are an important issue for the static random access memory (SRAM) memory device. In this paper, the design and analysis of CMOS based 9T SRAM cell in a variety of technologies is presented. The main focus of this review paper is to analyze 9T SRAM to test performance on several CMOS technologies (180nm, 90nm, 65nm, 45nm, 32nm, 14nm) with the help of a predictable technology (PTM) file. The butterfly curve method is used to examine the consistency of the SRAM bit cell in terms of static noise margin (SNM). It is clearly shown in this paper that as it progresses from 180nm to 14nm the delay decreases with stability.

Improved read/write assist mechanism for 10‐transistor static random access memory cell

AbstractThis paper presents a robust low‐power 10T SRAM cell (RLP10T) with a novel read/write assist mechanism, improving both read static noise margin (RSNM) and write static noise margin (WSNM) simultaneously. To assess its relative strength, we compared the proposed cell with recently published SRAM cells such as WRE8T, 10T‐P1, HFBS10T, WALP11T, and SE11T in 16‐nm CMOS technology node. The RLP10T cell shows 3.55/1.07 times higher/lower RSNM compared to the WRE8T/WALP11T cell and offers at least 1.10 times higher WSNM. Due to the presence of three series‐connected transistors in its read path, which includes a strong pull‐down transistor, the proposed design shows 1.23 times shorter read delay (TRA) than that of 10T‐P1/HFBS10T cell. The proposed cell incurs a penalty of high write delay (TWA) due to its long write path. However, it exhibits the fourth (second)‐best read (write) power, attributed to its single‐ended structure and lower read (write) frequency. It also dissipates acceptable leakage power due to its single‐bitline structure and the presence of stacked transistors in its read path and pull‐down path of one of the inverters in the cell core. Subjected to the severe process, voltage, and temperature variations, the RLP10T cell offers at least 1.31/1.09/1.03 times lower variability in RSNM/WSNM/TRA at VDD = 0.7 V, at the cost of 1.22 times area overhead compared to the WRE8T cell.

Gate All around CNTFET based Ternary Content Addressable Memory

This paper proposes a design of gate all around CNTFET based ternary content addressable memory (TCAM). TCAM cell is designed and simulated in HSPICE using top gated CNTFET (TG-CNTFET) & gate all around CNTTFET (GAA-CNTFET). Dual chirality technique is used to design TCAM cell i.e. different chirality for n-type CNTFET & p-type CNTFET which utilizes different threshold voltages and hence improve the performance. Comparative analysis has been done for various parameters viz. Static noise margin (SNM), delay, power and power delay product (PDP). It has been found that GAA-CNTFET based TCAM gives better SNM and power as compared to TG-CNTFET based TCAM, however TG-CNTFET based TCAM gives less delay. However overall PDP is less in GAA-CNTFET which make is suitable for circuit applications as compared to TG-CNTFET.

A Comparative Performance Analysis of 6T &amp; 9T SRAM Integrated Circuits: SOI vs. Bulk

This letter evaluates the performance of 6T &#x0026; 9T static random access memory (SRAM) cells, for data stability and power metrics, with the aim to compare silicon-on-insulator (SOI) and bulk CMOS technologies. Each SRAM topology was designed &#x0026; simulated in 180 nm 5 V XFAB-SOI and AMS-bulk processes, using optimized parameters and compatible devices. The fundamental variables analyzed were read noise margins, write trip current &#x0026; voltage as well as leakage current (LC) and static power dissipation (SPD) under process and temperature (PT) variations. The static noise margin (SNM) butterfly curve and N-curve methodologies were used to assess the mentioned parameters. Compared to bulk technology, the SRAM cells designed with SOI were found to have lower SPD &#x0026; LC, higher data stability, lower write ability, larger sensitivity to process variations and higher resilience to temperature deviations.

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

This paper presents a half-selected robust 12T bitcell with built-in write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improved by read decoupled. The writability is improved by data-dependent supply-cutoff write-assist. Both row and column f-selected bitcells can hold data stably during write operations. Simulation results based on a standard 55nm CMOS technology show that the read static noise margin of the proposed bitcell is 16.13x as that of the conventional 6T bitcell. Moreover, the write failure in the sub-threshold region is eliminated. In addition, the leakage consumption is improved by 15.7% compared with 6T bitcell.

Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET Technology

A novel 7T carbon nanotube field effect transistor (CNTFET)-based static random-access memory (SRAM) cell is proposed in this paper. Power and noise margin performances of the proposed SRAM cell is observed for write, hold and read operations. The power consumption and noise margin of the proposed SRAM cell is compared with the conventional 6T and 8T CNTFET-based SRAM cells. From the simulation, it is noted that the proposed 7T SRAM cell consumes lesser power and offers high static noise margin (SNM) compared to that of conventional 6T and 8T SRAM cells. The introduction of diode-based transistor structure improves the power and noise performance of the proposed SRAM cell. The effect of variation of parameters such as gate oxide thickness, dielectric constant, pitch, temperature, number of carbon nanotubes (CNT) and supply voltage on power and noise performance of proposed 7T SRAM cell is studied. Simulations were carried out with HSPICE simulation tool using Stanford University 32-nm CNTFET model.

A highly reliable radiation tolerant 13T SRAM cell for deep space applications

This paper proposes a highly reliable radiation-tolerant 13T (HRRT 13T) SRAM cell for deep-space applications. The proposed SRAM cell design can effectively tolerate radiation events. The design metrics of the proposed SRAM cell are compared with conventionally used SRAM cells like QUCCE 10T, QUCCE 12T and standard 6T SRAM cells. The proposed SRAM cell consumes 9.4% and 14% lesser hold power (HPWR) compared to QUCCE 10T and QUCCE 12T SRAM cells, respectively. The proposed SRAM cell exhibits 12.7%, 3.63% and 11.7% shorter read access time (TRA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at a nominal supply voltage (VDD) of 0.7 V. The proposed HRRT 13T SRAM cell exhibits higher read stability compared to other conventionally used SRAM cells. This has been validated by 2.92×, 2.33× and 2.06× higher read static noise margin (RSNM) exhibited by the proposed cell compared to the 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed SRAM cell exhibits high radiation tolerance capability compared to the conventionally used SRAM cells. This has been proved by 94.1%, 17.8% and 10.0% higher critical charge (QC) of the proposed cell compared to 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed cell achieves all these improvements at the expense of 1.05×, 1.38× and 1.36× longer write delay (TWA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at VDD = 0.7 V. Extensive simulations on SPICE using 16-nm CMOS technology are performed to validate the theoretical design of the proposed SRAM cell.

A Low-Power and High-Stability 8T SRAM Cell with Diode-Connected Transistors

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V or 200[Formula: see text]mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V). A [Formula: see text] memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of [Formula: see text] array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.

Study of CNTFETs as Memory Devices

In this paper we propose a procedure for the study of CNTFETs as memory devices. In particular we analyze the design of a 6-T SRAM, in order to evaluate the writing and reading times, in single and double supplies, the static noise margin, the static power consumption and the power-delay product. For these goals, we use a CNTFET model, already proposed by us. Then we apply the same procedure using the Stanford model in order to compare the obtained results. At last we apply the proposed analysis for the design of a 6-T SRAM in CMOS technology, showing the improvements obtained with CNTFET technology.

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

This paper proposes a novel design of ultra-low power radiation-hardened single-ended SRAM bit-cell using the gate-all-around CNT-MOSFET based-gate diffusion input method (GAA CNT-GDI) for application in radiation-prone terrestrial (low-orbit) environments, where resources of circuit’s power supply are limited. In the structure of bit-cell to improve read-/hold-stability and expand write-ability several schemes have been used such as asymmetric virtual ground gating, built-in read-assist and the multi-diameter/chirality for CNTs. Also, in order to investigate single/double upsets, injection circuit model using the structure of the T-connected pseudo resistors (TPRs) has been proposed. The results of extensive Monte-Carlo (MC) simulations to evaluate the proposed bit-cell indicate expand write/hold/read static noise margins about 12.5%, 3.8%, and 8.2%, other figure of merits (FoMs), such as performance, yield, variability (μ/σ) and critical charge about 6.4 %, 5.8 % and almost 1.19 times respectively compared to studied cell design in counterpart technologies. Moreover, the suggested bit-cell has more robustness against radiation-induced soft errors with high reliability of data storage in the presence of critical voltage conditions, and better results in terms of other comprehensive FoMs as compared to state-of-the-art bit-cells in the 16 nm technology. The proposed bit-cell in a real application is used to store data from two-layer quick-response (2LQR) code-based in safety-critical environments. The results show the better performance of bit-cell in terms of a comprehensive FoM, which provides more effective trade-off between the hardware efficiency and quality metrics to evaluate the appropriate accuracy in the pixel-by-pixel image as compared to other well-known counterpart designs. Finally, the simulation results have validated that the suggested memory architecture can be a suitable candidate for application in devices such as terrestrial satellites that require both high reliability and cost-effectiveness.

Static Response of Three-Dimensional and Printed Complementary Organic TFTs-Based Static Random-Access Memory

A three-dimensional (3-D) and printed static random-access memory (SRAM) based on complementary organic thin-film transistors is demonstrated. The SRAM exhibited the smallest area of 2.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the highest normalized static noise margin of 62%, and the maximum gain of 16.8 V/V compared to the reported values of organic SRAM cells. The transistors’ 3-D integration minimizes the cell area. The 3-D SRAM cell design enables us to match the strengths of transistors by modifying the dielectric thickness without changing the channel geometry. This high-performance complementary organic thin-film transistors-based SRAM shows its high application potential in large-scale and low-cost wearable intelligent electronics for data storage and processing.