Static Induction Transistor Research Articles

Improvements on voltage-resistant performance of bipolar static induction transistor (BSIT) with buried gate structure

The breakdown mechanism of power bipolar static induction transistor (BSIT) with buried gate structure is analyzed in depth. A power BSIT sample with high voltage-resistant capability has been designed and fabricated in this paper. The technological methods for improving high voltage performances are represented. The active region of BSIT is surrounded with a deep trench to avoid any probable influences of various defects on device performances. Two field-limiting ring-shape junctions and one channel termination ring-shape junction are arranged around the gate region to reduce the electric field intensity. The gate-source breakdown voltage BVGS of power BSIT has been increased to 110 V from previous value of 50–60 V, and its blocking voltage is increased to 1700 V. The optimal geometrical dimensions for achieving the maximum breakdown voltage BVGS and blocking voltage Vblock are also represented in the paper.

Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

In this article we review the fundamental properties and applications of sidewall GaAs tunnel junctions. Heavily impurity-doped GaAs epitaxial layers were prepared using molecular layer epitaxy (MLE), in which intermittent injections of precursors in ultrahigh vacuum were applied, and sidewall tunnel junctions were fabricated using a combination of device mesa wet etching of the GaAs MLE layer and low-temperature area-selective regrowth. The fabricated tunnel junctions on the GaAs sidewall with normal mesa orientation showed a record peak current density of 35 000 A cm-2. They can potentially be used as terahertz devices such as a tunnel injection transit time effect diode or an ideal static induction transistor.

Holographic study of thermal strains of microelectronic components

Results of a study of elements of solid-state electronics by holographic interferometry are presented. Examples of measurement of thermal strains of real products and control of engineering processes in the production of static induction transistors (SITs) and ultra-high frequency hybrid integrated circuits are given.

Improvement on the dynamical performance of a power bipolar static induction transistor with a buried gate structure

The failure of a bipolar static induction transistor (BSIT) often occurs in the transient process between the conducting-state and the blocking-state, so a profound understanding of the physical mechanism of the switching process is of significance for designing and fabricating perfect devices. The dynamical characteristics of the transient process between conducting-state and blocking-state BSITs are represented in detail in this paper. The influences of material, structural and technological parameters on the dynamical performances of BSITs are discussed. The mechanism underlying the transient conversion process is analyzed in depth. The technological approaches are developed to improve the dynamical characteristics of BSITs.

980 V, 33A Normally-Off 4H-SiC Buried Gate Static Induction Transistors

In this work, we succeeded in developing high performance normally-off SiC buried gate static induction transistors (SiC-BGSITs). To achieve the normally-off characteristics, design parameters around the channel region were optimized and process conditions were improved to realize these parameters. The off-state characteristic of the SiC-BGSIT showed an avalanche breakdown voltage of VBR=980 V at a gate voltage of VG=0 V. Furthermore, the leakage current at VD=950 V is lower than 0.5 μA. These results indicate that the BGSIT has a good normally-off characteristic. At VG=2.5 V, an on-resistance of 28.0 mΩ corresponding to the specific on-resistance of 1.89 mΩ•cm2 was obtained and the current rating was calculated as 33 A at a power density of 200 W/cm2 in the on-state characteristic.

GaN Power SIT의 설계변수에 따른 전기적 특성변화에 관한 연구

Gallium nitride (GaN), wide bandgap semiconductor, has attracted much attention because they are projected to have much better performance than silicon. In this paper, effects of design parameters change of GaN power static induction transistor (SIT) on the electrical characteristics (breakdown voltage, on resistance) were analyzed by computer simulation. According to the analyzed results, the optimization was performed to get power GaN SIT that has 600 V class breakdown voltage. As a result, we could get optimized 600 V class power GaN SIT that has higher breakdown voltage and lower On resistance with a thin (a several micro-meters) thickness of the channel layer.

Radiation Hardness Evaluation of SiC-BGSIT

In this study, we evaluated the radiation hardness of SiC Buried Gate Static Induction Transistors (SiC-BGSITs) and Si-based switching devices up to the absorbed dose of 10 MGy(SiO2). The on-voltage Von of Si-IGBT degraded excessively at the early stage of the irradiation (>~0.1 MGy(SiO2)) due to the bulk damage produced by Compton electrons like the gain degradation in Si bipolar transistors. The threshold voltage Vth of Si-MOSFET was very sensitive against the radiation due to the competing mechanism between the generation of the hole traps in the gate SiO2 and the SiO2/Si interface states. Moreover, the breakdown voltage VBR and leak current Ileak of MOSFET degraded significantly against the absorbed dose. While, the electrical properties of SiC-BGSIT was very stable even after the irradiation of 10 MGy(SiO2).

Crystalline Quality of Channel Regions in SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

We investigated the crystalline quality and electrical properties of the channel regions in 4H-SiC buried gate static induction transistors (SiC-BGSITs). To accurately determine the characteristics of the channel regions, we performed transmission electron microscopy and scanning spreading resistance microscopy. It was found that the channel regions have high crystalline quality and no significant fluctuations in doping concentration.

Improvements on radiation-hardened performance of static induction transistor

The radiation-hardened performances of static induction transistor (SIT) have been studied in depth in this paper. The effects of radiation of electron beam on the I-V characteristics, carrier distribution and potential distribution in the channel of SIT have been represented. A large number of electron-hole pairs are generated in the depletion region of reversely biased gate-channel PN junction. The radiation-generated electrons drift towards the drain region at high positive potential, while generated holes flow into gate region biased to the lowest potential. With the accumulation of holes in gate region, the gate potential is boosted, resulting in a decrease in the height of potential barrier in channel, and an increase in drain current. I-V characteristics of SIT in the presence of radiation have been theoretically derived, and compared with experimental results. With the increase in thickness of epitaxial layer, the radiation-hardened capability of SIT is continuously improved until the optimum thickness of 26 μm is reached. The optimum matching relationship among geometric, material and technological parameters has been represented to acquire excellent radiation-hardened performances of SIT.

Exponential dependence of potential barrier height on biased voltages of inorganic/organic static induction transistor

The exponential dependence of the potential barrier height ϕc on the biased voltages of the inorganic/organic static induction transistor (SIT/OSIT) through a normalized approach in the low-current regime is presented. It shows a more accurate description than the linear expression of the potential barrier height. Through the verification of the numerical calculated and experimental results, the exponential dependence of ϕc on the applied biases can be used to derive the I–V characteristics. For both SIT and OSIT, the calculated results, using the presented relationship, are agreeable with the experimental results. Compared to the previous linear relationship, the exponential description of ϕc can contribute effectively to reduce the error between the theoretical and experimental results of the I–V characteristics.

Short-Circuit Capability of SiC Buried-Gate Static Induction Transistors: Basic Mechanism and Impacts of Channel Width on Short-Circuit Performance

Fundamental short-circuit operations of silicon carbide static induction transistors with buried-gate structures (BGSITs) were experimentally clarified, with subsequent device simulations. The impacts of channel width and source length on short-circuit capabilities were investigated. In particular, a design concept of the channel width was proposed to improve the short-circuit energy without a serious increase in on-resistance. The maximum short-circuit capability of the fabricated BGSITs was 18 J/cm2 at room temperature, which shows excellent performance compared with that of conventional Si insulated-gate bipolar transistors.

Organic Electronics: Relaxation Time Controlled Devices

In present work the charge transport through the metal–semiconductor–metal (MIM), organic field-effect transistor (OFET) and organic static induction transistor (OSIT) is discussed on the basis of dielectric physics. The propagation of injected carriers is evaluated by the transmission line model and discussed for two- and three-electrodes systems individually. On the basis of this analysis we find different carrier transport mechanism: (i) the drift in electric field for MIM structure, (ii) interface charge propagation on the organic semiconductor–gate insulator interface for the OFET structure, and (iii) drift or interface limited charge transport in the OSIT structure. We show that the charge transport mechanism depends on the relaxation time on the interface.

Research of tripartite trench termination for power buried‐gate SIT

Purpose – The purpose of this paper is to introduce trench termination for high power buried‐gate static induction transistor (SIT) comprising three parts, which can inhibit the reverse leakage current substantially and paradisaical current. The simplified step‐etching process will also be discussed in detail.Design/methodology/approach – For power buried‐gate SIT, the trench termination comprises three grooves, gate electrode etching, mesa‐groove etching and the separated groove, respectively. The simplified step‐etching process is proposed to optimize the traditional technical processing.Findings – The tripartite trench termination of power SIT can inhibit the reverse leakage current, improve the gate‐source breakdown and increase the blocking voltage. The step‐etching process which is proposed for the first time, realizes the tripartite trench termination simultaneously which simplifies the traditional processes and is beneficial by protecting the surface of the die. The optimum etched depth of termina...

Evaluation of Refilled Channel Regions in 4H-SiC Buried Gate Static Induction Transistors

We evaluated the crystalline quality of the channel region in silicon carbide buried gate static induction transistors (SiC-BGSITs) by transmission electron microscopy (TEM) and scanning spreading resistance microscopy (SSRM). TEM observations revealed that no crystalline defects were generated in the channel region of SiC-BGSITs during epitaxial regrowth in trenches. The SSRM result indicated that the refilled channel region had a spreading resistance distribution of about ten times due to a high noise resulting from contact resistance. This noise was so high that we could not detect carrier density distributions from SSRM signals. However, on the basis of the leakage current and blocking characteristics of the SiC-BGSITs, we confirmed that there was no serious carrier density distribution that affected the device operation in the channel region.

Organic Inverter Using Monolithically Stacked Static Induction Transistors

We fabricated monolithic organic inverters using a stacked structure of two organic static induction transistors (SITs). The operating characteristics of a p-channel transistor load and p-channel transistor drive-type inverter in which pentacene films are employed as an organic semiconductor material are described. The gain transfer characteristics of a pentacene SIT inverter based on an enhancement-load/enhancement-drive layout showed a threshold voltage of approximately -1 V and a relatively large voltage gain of approximately 1.5. The advantages of this novel device structure are the controllability of the operational characteristics of each SIT and the simple device fabrication process.

Characterization of ion-implanted 4H-SiC Schottky barrier diodes

Ion-implantation layers are fabricated by multiple nitrogen ion-implantations (3 times for sample A and 4 times for sample B) into a p-type 4H-SiC epitaxial layer. The implantation depth profiles are calculated by using the Monte Carlo simulator TRIM. The fabrication process and the I-V and C-V characteristics of the lateral Ti/4H-SiC Schottky barrier diodes (SBDs) fabricated on these multiple box-like ion-implantation layers are presented in detail. Measurements of the reverse I-V characteristics demonstrate a low reverse current, which is good enough for many SiC-based devices such as SiC metal–semiconductor field-effect transistors (MESFETs), and SiC static induction transistors (SITs). The parameters of the diodes are extracted from the forward I-V and C-V characteristics. The values of ideality factor n of SBDs for samples A and B are 3.0 and 3.5 respectively, and the values of series resistance Rs are 11.9 and 1.0 kΩ respectively. The values of barrier height φB of Ti/4H-SiC are 0.95 and 0.72 eV obtained by the I-V method and 1.14 and 0.93 eV obtained by the C-V method for samples A and B respectively. The activation rates for the implanted nitrogen ions of samples A and B are 2% and 4% respectively extracted from C-V testing results.

GaN Power FET 모델링에 관한 연구

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340 V breakdown voltage. The channel thickness was 3 urn and the channel doping concentration is . And we carried out thermal characteristics, too.

Improvements on high voltage performance of power static induction transistors

A novel structure for designing and fabricating a power static induction transistor (SIT) with excellent high breakdown voltage performance is presented. The active region of the device is designed to be surrounded by a deep trench to cut off the various probable parasitical effects that may degrade the device performance, and to avoid the parallel-current effect in particular. Three ring-shape junctions (RSJ) are arranged around the gate junction to reduce the electric field intensity. It is important to achieve maximum gate-source breakdown voltage BVGS, gate-drain breakdown voltage BVGD and blocking voltage for high power application. A number of technological methods to increase BVGD and BVGS are presented. The BVGS of the power SIT has been increased to 110 V from a previous value of 50–60 V, and the performance of the power SIT has been greatly improved. The optimal distance between two adjacent ring-shape junctions and the trench depth for the maximum BVGS of the structure are also presented.

Effect of gate insulating layer on organic static induction transistor characteristics

Organic static induction transistors, which have relatively short vertical channels, are attractive devices for their low operating voltage and high operating speed. However, a gate voltage larger than the Schottky barrier potential usually leads to a large gate leakage current and thus poor device performance. To limit the gate leakage current, we considered adding insulating layers around the gate electrode. The oxidization of aluminum during a physical vapor deposition process was used to form insulating layers around the gate electrode. The results demonstrate that by appending gate insulating layers, gate leakage currents can be effectively reduced and device characteristics, especially the on/off ratio, can be improved.

Vertical organic light-emitting transistors with an evaporated Al gate inserted between hole-transporting layers

Similar to the configuration of static induction transistor (SIT), vertical organic light-emitting transistors (VOLETs) with an evaporated Al gate inserted between hole-transporting layers were fabricated and their static characteristics were characterized. By using Alq 3 as the emissive layer, the basic transistor characteristics of the VOLETs were compared with two organic hole-transporting layers, N, N′-diphenyl- N,N′-bis(3-methylphenyl)-(1,1′-biphenyl)-4,4′-diamine (TPD) and N,N′-bis-(1-naphthyl)- N,N′-diphenyl-1,1′-biphenyl-4,4′-diamine (NPB). Our experimental data show that the intensity of emission from VOLETs can be tuned by adjusting gate voltages. The emission intensity of device ITO/TPD/Al/TPD/Alq 3/Al decreases by increasing the applied gate voltages, showing an operation in depletion mode, however, it shows the operation in enhancement mode for VOLET device ITO/NPB/Al/NPB/Alq 3/Al. Further, the reasons for these two different phenomena were discussed in terms of the dielectric constant of materials, carrier mobility and energy barriers at electrode/organic interface.