Static Circuits Research Articles

Single-polarity dual-rail logic

Static CMOS circuit techniques are widely used for processor designs. The authors introduce an add-on technique for high-speed static circuit realisation. The underlying processes of this technique, a time-shifting process and a collision process, are described and the performance of the resulting circuitry is compared with that of the conventional version. The new technique, which utilises a single polarity signal on a separate path, achieves ~15% delay reduction compared with the conventional static CMOS design.

CMOS translinear circuits for minimum supply voltage

Three basic translinear circuit topologies are modified for use at low supply voltage. They are: (1) the balanced translinear loop; (2) the alternating translinear loop; and (3) the instantaneous-companding integrator. The key to this work is the constructive use of nonsaturated MOS transistors operating in weak inversion. This provides two improvements. First, circuit operation is extended to low supply voltage. Second, accurate realization is enabled since the circuits become immune to MOS body-effect. The proposed techniques are suitable for static and dynamic analog signal processing circuits in mixed-signal chips fabricated in digital CMOS technology and operating at the minimum possible supply voltage.

Synthesis of log-domain filters from first-order building blocks

Log-domain filters are an important class of current-mode circuits having large-signal linearity and increased tuning range over voltage-mode filter circuits of similar complexity. In this paper we describe synthesis of a single-ended, first-order filter circuit from static and dynamic translinear circuit principles, and show how higher-order filters can be easily constructed from the first-order building block. We address additional issues related to low-frequency (audio-frequency) filter design and present results measured from test circuits and a complete 15-channel filterbank system fabricated in 2 μm and 1.2 μm BiCMOS processes.

A scannable pulse-to-static conversion register array for self-timed circuits

This paper describes the design and hardware results of a scannable pulse-to-static conversion register array for self-timed circuits. The circuits include a self-timed control circuit and a 64-bit register array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control block allows it to require only one system clock input. The evaluation, reset, and write-enable controls are all generated within the control macro. The register array is a level-sensitive scan design, which is compatible and complies with SRCMOS test modes. This type of register array can facilitate the synchronous/asynchronous interfaces, pipelined operation, power management, and testing of advanced digital systems employing a mixture of static and dynamic circuits to achieve low power and high performance.

An energy-efficient noise-tolerant dynamic circuit technique

Noise in deep submicron technology combined with the move toward dynamic circuit techniques have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. The average noise threshold energy (ANTE) and the energy normalized ANTE (NANTE) metrics are proposed to quantify the noise immunity and energy efficiency, respectively. Simulation results in 0.35-/spl mu/m CMOS for NAND gate and full-adder designs indicate that the proposed technique improves the ANTE and NANTE by 2/spl times/ and 1.4/spl times/ over conventional domino circuits. The improvement in the NANTE is 11% higher than the existing noise-tolerance techniques. Furthermore, the proposed technique has a smaller area overhead (36%) as compared to static circuits whose area overhead is 60%. Also presented in this paper is an ASIC developed in 0.35-/spl mu/m CMOS to evaluate the performance of the proposed technique. Experimental results demonstrate a 27% average improvement in noise immunity over conventional dynamic circuits.

Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation

We describe the use of symmetry for verification of transistor-level circuits by symbolic trajectory evaluation (STE). We present a new formulation of STE which allows a succinct description of symmetry properties in circuits, Symmetries in circuits are classified as structural symmetries, arising from similarities in circuit structure, data symmetries, arising from similarities in the handling of data values, and mixed structural-data symmetries. We use graph isomorphism testing and symbolic simulation to verify the symmetries in the original circuit, Using conservative approximations, we partition a circuit to expose the symmetries in its components, and construct reduced system models which can be verified efficiently, Introducing X-drivers into switch-level circuits simplifies the task of creating conservative approximations of switch-level circuits, Our empirical results show that exploiting symmetry with conservative approximations can allow one to verify systems several orders of magnitude larger than otherwise possible. We present results of verifying static random access memory circuits with up to 1.5 Million transistors,.

Scattering extraction of ions at CRYRING for SEU testing

A measuring station has been built at the CRYRING heavy ion accelerator to test the Single Event Upset (SEU) phenomena in working Static RAM circuits. The setup extracts the beam using Rutherford scattering and the ions are monitored with a BaF2 scintillator. SEU measurements have been performed for standard bulk CMOS memory circuits.

Dynamic modeling of high power static switching circuits in the dq-frame

With the proliferation of static switching circuits in power systems, there is a need to understand not only their steady-state behaviour but their dynamic interaction with the network as well. Analysis is difficult due to the nonlinear nature of switching processes associated with such devices. Linear, time-invariant (LTI) dynamic models are needed for standard analytical tools such as eigenanalysis for the study of inter-area as well as higher frequency modes of the system. To this end, LTI small-signal dynamic models are developed for high power static switching circuits in a synchronous rotating dq-reference frame. Two conventional devices are chosen for study: a thyristor controlled series capacitor (TCSC) and a HVDC power converter. The proposed models are shown to represent the dynamic response of the static switching circuits to nominal changes in operating point. In particular, the damping characterizing the dynamic behaviour of the TCSC is shown to vary significantly with operating point. This accounts for the observed responses arising from field tests and simulations but not accounted for by the quasi-static model. On the other hand, the damping characterizing the dynamic behaviour of the HVDC converter is shown to vary little with operating point. The linearized models are validated by digital time-domain simulation of the nonlinear static switching circuits.

A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors

In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well.

Nonlinear analysis of noise in static and dynamic translinear circuits

For translinear filters, or log-domain filters, calculation of the maximal signal-to-noise-ratio, an important filter specification, is not trivial, due to the inherent companding behavior and the nonstationary nature of the transistor noise sources. To address this issue, a nonlinear noise analysis method is proposed. Based on large-signal calculations, expressions for the first-order noise and signal-noise intermodulation terms are computed. The procedure is generally applicable both to static and dynamic translinear circuits, as illustrated by a number of generic examples.

A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file

A two-write-port, six-read-port, 32/spl times/64-bit register file has been designed for 2.5-V 0.5-/spl mu/m CMOS technology, using primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test compatible. The fabricated register file occupies an area of 1.84/spl times/1.55 mm/sup 2/, and the cell size is 21.6/spl times/30 /spl mu/m/sup 2/. The high-performance register file is implemented in a multiblock structure consisting of subarrays and associated multiplexing circuits. For a given read port, the outputs of all multiplexer circuits are dotted together to form a single global output. A quasi-global approach is used for reset pulse generation and timing control circuits to reduce area overhead. The output pulse width is controlled by a chopper circuit. The write-port operation is achieved by the combination of static data input and dynamic control circuits. The write-path circuits employ the advantages of the input isolation technique. Individual write-enable pulses applied to respective input ports of a multiport register-file cell are effective to establish a priority among those input ports. The present design provides an effective input isolation/decoupling circuit technique that allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in an effective input isolation scheme. Testing has shown all eight ports to be functional. The measured read access time was 1.1 ns, and read operation has been obtained at cycle times as short as 1.9 ns. The register file has been shown to be tolerant to a very wide range of input pulse widths yet delivers tightly controlled outputs.

A 150-MHz translinear phase-locked loop

This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode "log-domain" oscillator in a classical PLL topology to obtain these features. The PLL has been fabricated in a 0.6-/spl mu/m 12-GHz BiCMOS process, and measured results show a capture range of 15 MHz at a center frequency of 150 MHz. The circuit operates from a single 3-V supply and draws 6 mA at 150 MHz. A phase noise of -80 dBc/Hz at 1 kHz offset was obtained with the PLL locked onto an input reference frequency of 151 MHz. The PLL response to a frequency-modulated input has also been examined, and the demodulated output at 100 KHz showed less than -30-dB total harmonic distortion.

Exploring the design space of mixed swing quadrail for low-power digital circuits

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2/spl times/ improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 /spl mu/m process are presented to demonstrate up to 2,92/spl times/ energy/operation savings for optimized mixed swing circuits compared to static CMOS.

General current-mode analysis method for translinear filters

Log-domain or translinear filters are regarded as being a promising alternative in the area of low-voltage filter design. To date, most publications have reported on synthesis of translinear filters. Although synthesis is more powerful than analysis, it must go together with a generally applicable analysis method in the same domain. In this paper, a general current-mode analysis method is proposed. By using a current-mode approach, we stay close to the existing theory on static translinear circuits, which might be beneficial in developing a general, possibly more powerful synthesis method.

Low-power double-edge triggered flipflop

Low-power double-edge triggered flipflops are presented using weak feedback transistors which allow purely n-type transmission gates, but without static-power consumption. The switching capacitance of the weak transistors is minimised by using permanently ON transistors in series as resistive devices. Both static and semi-static circuits are presented.

A 400-MHz S/390 microprocessor

A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-/spl mu/m L/sub eff/ CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm/spl times/17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units (IUs), two fixed point units (FXUs), two floating point units (FPUs), a buffer control element (BCE) with a unified 64-KB L1 cache, and a register unit (RU). The microprocessor dispatches one instruction per cycle. The dual-instruction, fixed, and floating point units are used to check each other to increase reliability and not for improved performance. A phase-locked-loop (PLL) provides a processor clock that runs at 2/spl times/ the system bus frequency. High-frequency operation was achieved through careful static circuit design and timing optimization, along with limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. Timing-driven synthesis and placement of the control logic provided the maximum flexibility with minimum turnaround time. Extensive use of self-resetting CMOS (SRCMOS) circuits in the on-chip L1 cache provides a 2.0-ns access time and up to 500 MHz operation.

A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file

We describe a 640-ps read access, 16-word by 64-b, three-port register file fabricated in 0.25-/spl mu/m effective channel length CMOS technology. It features the capability to perform a write followed by a read in the same cycle at frequencies above 500 MHz. High speed is achieved by using a novel cell and array structure. Static circuit design is used exclusively throughout the entire register file and is optimized for high-speed operation. Measured results of the same-cycle read-after-write demonstrate register file operations at 625 MHz. Additionally internal probe measurements of the read access path components are presented and compared with circuit simulations.

Performance of CMOS differential circuits

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are performed in terms of area, number of transistors, and propagation delay. Results indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts. Further improvement in circuit performance can be achieved by choosing an appropriate differential structure to match logic structure being implemented. Second, even though the circuit techniques such as differential split-level perform better, they may not be widely accepted mainly because of the increase in circuit complexity and cost. Lastly, the self-timed dynamic differential circuit techniques yield considerable improvement in speed without having the problems of charge distribution or race conditions typically associated with the conventional single-ended domino circuit technique.

Switching time bifurcations in a thyristor controlled reactor

Thyristor controlled reactors are high power switching circuits used for static VAR control and the emerging technology of flexible AC transmission. The static VAR control circuit considered in the paper is a nonlinear periodically operated RLC circuit with a sinusoidal source and ideal thyristors with equidistant firing pulses. This paper describes new instabilities in the circuit in which thyristor turn off times jump or bifurcate as a system parameter varies slowly. The new instabilities are called switching time bifurcations and are fold bifurcations of zeros of thyristor current. The bifurcation instabilities are explained and verified by simulation and an experiment. Switching time bifurcations are special to switching systems and, surprisingly, are not conventional bifurcations. In particular, switching time bifurcations cannot be predicted by observing the eigenvalues of the system Jacobian. We justify these claims by deriving a simple formula for the Jacobian of the Poincare map of the circuit and presenting theoretical and numerical evidence that conventional bifurcations do not occur.

Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching

This paper presents an accurate estimation of signal activity at the internal and output nodes of static and domino CMOS combinational logic circuits. The methodology is based on a stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In static combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented a technique to calculate signal probability and switching activity of static CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered, the switching activities at the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results. On the other hand, domino circuits are free of spurious transitions. Based on the precharge scheme of domino circuits, a technique for estimation of signal activity is presented. The results are within 1% of logic simulation results.