Standard Design Flow Research Articles

BTI and HCI first-order aging estimation for early use in standard cell technology mapping

The performance degradation in digital integrated circuit (IC) caused by BTI and HCI aging effects has increased significantly at each new technology node, as well as their importance in terms of circuit reliability throughout the entire circuit lifetime. This work proposes an aging design cost estimation method to be exploited in standard cell IC design flow. This method must be simple and fast, although not so accurate, to be suitable for the intense interactive process during the technology mapping in the logic synthesis phase. The proposed aging cost has been verified and validated through SPICE simulations carried out over a large number of CMOS gates.

Design and Validation of Configurable Online Aging Sensors in Nanometer-Scale FPGAs

In current CMOS nanometer technologies, aging effects may appear after relatively short operating times, compared to the expected lifetime of circuits. Therefore, there is an increasing need for on-chip aging monitoring, especially in high-performance, safety critical systems. This paper presents a programmable aging sensor that can be embedded in field-programmable gate array (FPGA)-based designs, using standard resources available in those devices and with minimal impact on the standard FPGA design flow. Given the limited amount of resources required by the sensor, it can be instantiated not only in the critical paths of a circuit, but also in those that may be identified to be more likely affected by aging effects. Experimental results, obtained in circuits of increasing complexity (where several sensors need to be used), are presented and discussed, demonstrating the good performance of the proposed sensor, as well as its low cost in terms of area overhead and power consumption. Results of aging experiments based on the standard US MIL-STD-883 Method 1015.50 “Burn-In Test” are also reported, demonstrating that the effect of aging on the sensor is negligible compared to that on the circuit under test, which is a key point for practical applicability. The proposed approach provides a novel and efficient solution to the specific FPGA design problems in this context, which are different from those addressed in application-specific integrated circuit design.

Low Power Decoding of LDPC Codes

Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging area especially when power efficient solutions are needed. Implementation details are given for an LDPC decoding algorithm, termed adaptive threshold bit flipping (ATBF), designed for low complexity and low power operation. The ATBF decoder was implemented in 90 nm CMOS at 0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.

A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect

Strain technology has become indispensable for present CMOS integrated circuits (ICs) as the feature size of transistor shrinks. In the meantime, stress-induced variation has also become an unavoidable problem. Unintentional stress, such as shallow trench isolation (STI)- induced stress, is one of the main variation sources and is strongly layout dependent. In this paper, a new 2-D layout-dependent STI stress model and related device parameter model are proposed. The stress model captures layout parameters along both the longitudinal direction and the transverse direction, based on which channel stress induced by STI is derived. Device parameters including threshold voltage, mobility, and saturation velocity are then modified according to several analytical models. The model can be integrated into standard CMOS IC design flow. By comparing with TCAD simulation and experiments with 65-nm process, it shows that the new model can give a better prediction accuracy than the original process design kit.

Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices

Hybrid integration of CMOS and nonvolatile memory (NVM) devices has become the foundation for emerging nonvolatile memory-based computing. The primary challenge to validate hybrid memory system with both CMOS and NVM devices is to develop a SPICE-like simulator that can simulate the dynamic behavior accurately and efficiently. Since memristor, spin-transfer-toque magnetic-tunneling-junction (STT-MTJ) and phase-change-memory (PCM) devices are the most promising candidates of next generation of NVM devices, it is under great interest in including these new devices in the standard CMOS design flow. The previous approaches either ignore dynamic effect without consideration of internal states for dynamic behavior, or need complex equivalent circuits to represent those devices. This paper proposes a new modified nodal analysis for NVM devices with identified internal state variables for dynamic behavior. As such, compact SPICE-like implementation can be derived for all three new NVM devices in the design of large-scale memory circuits. As demonstrated by a number of examples on hybrid memory circuits with both CMOS and NVM devices, our newly developed SPICE-like simulator can capture dynamic behaviors of memristor, STT-MTJ and PCM devices, and can also reduce CPU runtime by 20-69 times when compared to the previous equivalent circuit based approaches.

Optimization of the design flow of the system on a K64-RIO crystal manufactured using the 0.18 μm technology

In the process of developing a high-performance system on a crystal, the standard design flow proposed by CAD suppliers has been substantially changed and expanded due to the application of new design methods and the use of independently developed custom blocks. These changes made it possible to solve the following important problems: optimization of the area, with the performance at the stage of synthesis being preserved up to 20%, which improves the quality of the placement and design routability during layout designing; construction of a power grid providing a voltage drop not greater than 6.6% of the rated voltage; automation of the process of reaching the required performance and optimization of a number of layout stages yielding a decrease by a factor of 2–3 in the time of routing and improving the design quality from the standpoint of such parameters as noise immunity and performance.

Efficient multi-level fault simulation of HW/SW systems for structural faults

In recent technology nodes, reliability is increasingly considered a part of the standard design flow to be taken into account at all levels of embedded systems design. While traditional fault simulation techniques based on low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to properly cope with the complexity of modern embedded systems. Moreover, they do not allow for early exploration of design alternatives when a detailed model of the whole system is not yet available, which is highly required to increase the efficiency and quality of the design flow. Multi-level models that combine the simulation efficiency of high abstraction models with the accuracy of low-level models are therefore essential to efficiently evaluate the impact of physical defects on the system. This paper proposes a methodology to efficiently implement concurrent multi-level fault simulation across gate- and transaction-level models in an integrated simulation environment. It leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This combination of different models allows to accurately evaluate the impact of faults on the entire hardware/software system while keeping the computational effort low. Moreover, since only selected portions of the system require low-level models, early exploration of different design alternatives is efficiently supported. Experimental results obtained from three case studies are presented to demonstrate the high accuracy of the proposed method when compared with a standard gate/RT mixed-level approach and the strong improvement of simulation time which is reduced by four orders of magnitude in average.

Synthesis of AMBA AHB from formal specification: a case study

The standard hardware design flow involves: (a) design of an integrated circuit using a hardware description language, (b) extensive functional and formal verification, and (c) logical synthesis. However, the above-mentioned processes consume significant effort and time. An alternative approach is to use a formal specification language as a high-level hardware description language and synthesize hardware from formal specifications. Our work is a case study of the synthesis of the widely and industrially used AMBA AHB protocol from formal specifications. Bloem et al. presented the first formal specifications for the AMBA AHB Arbiter and synthesized the AHB Arbiter circuit. However, in the first formal specification some important assumptions were missing. Our contributions are as follows: (a) We present detailed formal specifications for the AHB Arbiter incorporating the missing details, and obtain significant improvements in the synthesis results (both with respect to the number of gates in the synthesized circuit and with respect to the time taken to synthesize the circuit), and (b) we present formal specifications to generate compact circuits for the remaining two main components of AMBA AHB, namely, AHB Master and AHB Slave. Thus with systematic description we are able to automatically and completely synthesize an important and widely used industrial protocol.

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications

Ultra-low voltage is now a well-known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. At 0.33V, it performs at 600 kHz with a dynamic energy consumption reduced by a factor 14x from nominal 1.1V. Based on this design, experiments, and preliminary silicon results, two additional libraries were developed in order to enhance future ultra-low voltage circuit performance.

An Implementation of Integral Low Power Techniques for Modern Cell-Based VLSI Designs

Recent research has proposed several low-power design techniques for VLSI circuitry in nano-scale CMOS era. However, these techniques always involve custom layout design or novel Electronic Design Automation (EDA) flows. In this paper essential low power techniques such as voltage separation, body bias and power switch are implemented in existent place and route (P&R) tools. These techniques enable the possibility to integrated low power techniques into standard Cell-Based physical design flow. The result of these research shows a little overhead in design procedure equally area overhead compare with fully custom design flow. The proposed low power design techniques can be cooperated with modern power management system to enable the power reduction in targeting circuitry with small implementation overheads. disconnect power supply of functional block. This is achieved by connecting a transistor in series with the power supply of the block (3). In practice, a network of power switch may be necessary to efficiently control and reduce leakage power. Another dynamic technique, body bias, needs dynamically changing the body bias applied to the block (4). During active mode, forward body bias (FBB) is applied to increase the operating frequency. Alternately, reverse body bias (RBB) can be applied during idle mode for further leakage savings. This body bias technique can be combined with a power switch to provide even further leakage power savings. However, the majority of low power design circuits are implemented with Fully-Custom design. In order to automate design phase and satisfy the demand of Time-To-Market requirement, integrating low power techniques into Cell- Based physical design flow is essential. In order to apply the benefits offered by low leakage techniques into Cell-Based design, some physical design issues must take into considerations. Therefore, the general physical design flow must be modified for the integrating low power techniques into physical design. In this paper, a low power physical design methodology is presented. By using this low power design methodology, a Cell-Based design circuit with low power techniques features is available. Our goal is to create a regular physical design flow utilizing existent EDA tool.

A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders

A low-complexity message-passing algorithm, called Split-Row Threshold, is used to implement low-density parity-check (LDPC) decoders with reduced layout routing congestion. Five LDPC decoders that are compatible with the 10GBASE-T standard are implemented using MinSum Normalized and MinSum Split-Row Threshold algorithms. All decoders are built using a standard cell design flow and include all steps through the generation of GDS II layout. An Spn = 16 decoder achieves improvements in area, throughput, and energy efficiency of 4.1 times, 3.3 times, and 4.8 times, respectively, compared to a MinSum Normalized implementation. Postlayout results show that a fully parallel Spn = 16 decoder in 65-nm CMOS operates at 195 MHz at 1.3 V with an average throughput of 92.8 Gbits/s with early termination enabled. Low-power operation at 0.7 V gives a worst case throughput of 6.5 Gbits/s-just above the 10GBASE-T requirement-and an estimated average power of 62 mW, resulting in 9.5 pj/bit. At 0.7 V with early termination enabled, the throughput is 16.6 Gbits/s, and the energy is 3.7 pJ/bit, which is 5.8× lower than the previously reported lowest energy per bit. The decoder area is 4.84 mm2 with a final postlayout area utilization of 97%.

Floating-Point FPGA: Architecture and Modeling

This paper presents an architecture for a reconfigurable device that is specifically optimized for floating-point applications. Fine-grained units are used for implementing control logic and bit-oriented operations, while parameterized and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and floating-point operations are used to implement datapaths. In order to facilitate comparison with existing FPGA devices, the virtual embedded block scheme is proposed to model embedded blocks using existing field-programmable gate array (FPGA) tools. This methodology involves adopting existing FPGA resources to model the size, position, and delay of the embedded elements. The standard design flow offered by FPGA and computer-aided design vendors is then applied and static timing analysis can be used to estimate the performance of the FPGA with the embedded blocks. On selected floating-point benchmark circuits, our results indicate that the proposed architecture can achieve four times improvement in speed and 25 times reduction in area compared with a traditional FPGA device.

Constrained Asynchronous Ring Structures for Robust Digital Oscillators

On-chip digital oscillators are ubiquitous in every communication applications like in RF architectures or intra-chip communication systems. Actually, their integration to the standard CMOS design flow, their ability to generate high-frequency signals, as well as their configurability make them really attractive for designers. However, these kinds of digital oscillators suffer from their sensitivity to any process, voltage, or temperature variations. Self-timed systems are usually considered robust to these kinds of variations. This paper proposes the use of self-timed ring structures for generating high-resolution timing signals. One of the main difficulties when designing such oscillators is to avoid burst oscillating modes and produce uniformly spaced events in order to act as a periodic time-base. Based on a high-level ring model, enriched with stage switching timing information, the temporal behavior of oscillating self-timed rings is studied and their robustness to process variability is evaluated. Several ring architectures are explored to take advantage of complex combination of stages I/Os and it is shown that one can tune a tradeoff between oscillation period and signal stability. In addition, the paper provides designers with the ability to easily prevent burst oscillating modes by applying a very tractable ring design rule. Electrical simulations demonstrate the correctness and efficiency of the approach.

A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications

We present an architecture for a synthesizable datapath-oriented FPGA core that can be used to provide post-fabrication flexibility to an SoC. Our architecture is optimized for bus-based operations and employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. The primary motivation for this architecture is to provide an efficient mechanism to support on-chip debugging. The fabric can also be used to implement other datapath-oriented circuits such as those needed in signal processing and computation-intensive applications. We evaluate our architecture using a set of benchmark circuits and compare it to previous fabrics in terms of area, speed, and power.

Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs

This paper presents an approach to reduce substrate cross-talk noise between noisy and sensitive circuitry in mixed-signal integrated circuits at different stages of design and layout development. Silencer! a new, fully automated, schematic-driven substrate noise coupling analysis tool is introduced to accomplish this task. The tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. Two different methods, fast scalable macro-models and a boundary element solver are integrated into Silencer!. These methods allow extractions of a substrate network from geometric layout information. Simulation results obtained with Silencer! are accurate to within 10% of measured integrated circuits

Dynamic State-Retention Flip-Flop for Fine-Grained Power Gating With Small Design and Power Overhead

Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps

A digital design flow for secure integrated circuits

Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digital complementary metal-oxide-semiconductor (CMOS) gates. This paper presents a digital very large scale integrated (VLSI) design flow to create secure power-analysis-attack-resistant ICs. The design flow starts from a normal design in a hardware description language such as very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) or Verilog and provides a direct path to an SCA-resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. The basis for power analysis attack resistance is discussed. This paper describes how to adjust the library databases such that the regular single-ended static CMOS standard cells implement a dynamic and differential logic style and such that 20 000+ differential nets can be routed in parallel. This paper also explains how to modify the constraints and rules files for the synthesis, place, and differential route procedures. Measurement-based experimental results have demonstrated that the secure digital design flow is a functional technique to thwart side-channel power analysis. It successfully protects a prototype Advanced Encryption Standard (AES) IC fabricated in an 0.18-mum CMOS

High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cells

This paper presents a high-performance asynchronous template, single-track full-buffer (STFB), which achieves close to full-custom performance using a standard cell design flow and industry standard CAD tools to perform schematic capture, simulation, cell layout, and automatic placement and routing. This template and flow is demonstrated and evaluated with the implementation of a 64-bit asynchronous prefix adder, and its test circuitry, using the TSMC 0.25-/spl mu/m process. The 64-bit asynchronous prefix adder layout requires 0.96 mm/sup 2/ and the entire 260-k transistor test chip reaches a measured throughput of 1.45GHz. The design demonstrates that the STFB template can yield three times higher throughput with approximately half of the area of comparable quasi-delay-insensitive (QDI) templates, requires less timing assumptions than ultra-high-speed GasP bundled-data circuits, and can be designed with an automated place and route flow.

On-Chip Millionfold Sample Stacking Using Transient Isotachophoresis

We present a simple and robust isotachophoresis (ITP) method that can be integrated with microchip-based capillary electrophoresis (CE) devices to achieve millionfold sample stacking. We performed an experimental parametric study to show the effects of initial sample ion concentration, leading ion concentration, and trailing ion concentration on ITP stacking. We also discuss the usefulness and limitations of a simple one-dimensional nondispersive model and a scaling analysis for dispersion rate. We found that a single-column ITP configuration together with electroosmotic flow suppression and high leading ion concentration provide high-performance ITP and can be integrated readily with CE separation. We demonstrated detection of trace of 100 fM Alexa Fluor 488 (signal-to-noise ratio of 11) with a concentration increase of a factor of 2 x 10(6). Application of our ITP/CE protocol to the stacking and separation of negatively charged fluorescent tracers (Alexa Fluor 488 and bodipy) resulted in a concentration increase of 6.4 x 10(4) and a signal increase of 4.5 x 10(5). The ITP/CE protocol can be performed with a standard microchannel cross design or simple flow control. The method can be implemented with available off-the-shelf chip systems using off-the-shelf voltage control systems and buffer chemistries.

GALS Test Chip on 130nm Process

We present a Globally Asynchronous Locally Synchronous test chip fabricated on a 130nm silicon process. The primary design goals of this chip were to measure the stability of local clocks on a deep submicron process technology, evaluate difficulties using GALS in a standard design flow, and to measure power consumption. The original Asynchronous Wrapper building blocks were used to construct a configurable data pipeline that can be tuned to emulate the operation of many different types of algorithms.