Abstract
The performance degradation in digital integrated circuit (IC) caused by BTI and HCI aging effects has increased significantly at each new technology node, as well as their importance in terms of circuit reliability throughout the entire circuit lifetime. This work proposes an aging design cost estimation method to be exploited in standard cell IC design flow. This method must be simple and fast, although not so accurate, to be suitable for the intense interactive process during the technology mapping in the logic synthesis phase. The proposed aging cost has been verified and validated through SPICE simulations carried out over a large number of CMOS gates.
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