Standby Power Dissipation Research Articles

A 2.2 W, 80 MHz superscalar RISC microprocessor

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 /spl mu/m, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1/spl times/, 2/spl times/, 3/spl times/, and 4/spl times/ are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10/sup 4/, and the source-drain leakage current is decreased by a factor of 10-10/sup 2/ compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs. >

Charge-neutralized differential amplifiers

A new broadbanding technique for small signal, bipolar differential amplifiers is analytically developed. The new design method significantly improves the circuit gain-bandwidth product of a conventional differential pair without increasing standby power dissipation. “Charge neutralization,” as introduced in this work, is an extension circuit unilateralization theory. It exploits the ability of a mature monolithic fabrication process to control the relative geometries of two otherwise identical active devices. The new design theory has been thoroughly researched for junction isolated and dielectrically isolated silicon bipolar processes. But preliminary work suggests that it offers especially dramatic improvements in frequency response when utilized in conjunction with bipolar SOI technologies.

One-transistor GaAs MESFET- and JFET-accessed dynamic RAM cells for high-speed medium density applications

Theoretical and experimental work that presents the possibility for a high-speed, low-power one-transistor room-temperature dynamic RAM (DRAM) technology in GaAs is discussed. Isolated storage capacitors have demonstrated over 20 min of storage time at room temperature with charge densities comparable to that obtained with planar silicon technology. One-transistor MESFET- and JFET-accessed DRAM cells have been fabricated and operated at room temperature and above. The standby power dissipation of these first cells is only a small fraction of the power dissipated by the best commercial GaAs static RAM (SRAM) cells. >

On the analysis and design of CMOS-bipolar SRAMs

The design and operation of a CMO-bipolar SRAM cell, which incorporates cross-coupled CMOS and n-p-n access transistors, is discussed. A column circuitry to accompany this cell is proposed. Simulation results attributing column access time, standby power dissipation, and active power dissipation of 6-8 ns, 6.5 nW/bit, and 4 mW/b, respectively, for a cell area of ~450 /spl mu/m/SUP 2/, suggest the suitability of this approach for applications requiring density, performance, and moderate power.

An experimental 5-V-only 256-kbit CMOS EEPROM with a high-performance single-polysilicon cell

A novel single-polysilicon EEPROM cell, called DIFLOX (diffused layer controlled floating-gate-type cell with thin oxide), has been used in this experimental memory. The floating-gate voltage is controlled by two thin-oxide capacitors coupled with two N/SUP +/ diffused layers: the drain and the control gate. Its size is reduced to 86.25 /spl mu/m/SUP 2/ by 1.2-/spl mu/m photolithography and scaled transistors with 1.4-/spl mu/m gate length. For programming time reduction, a page-mode programming scheme was used. Successive data of up to 16 bytes can be loaded into internal storage and programmed simultaneously. All high voltages needed to perform the ERASE/PROGRAM function are generated internally, and two kinds of timers were designed using an improved switched-capacitor technique. Owing to the open-bit-line scheme, cell data were detected with high sensitivity in spite of the large-bit-line and word-line parasitic capacitance. The EEPROM typically achieves a 150-ns address access time, with an 80-mW active and 1-/spl mu/W standby power dissipation. It was successfully fabricated in a single-polysilicon and single-metal CMOS process. The chip is 7.33/spl times/6.23 mm/SUP 2/ and is packed into the DIP 28 pin, which is pin-to-pin compatible to a 256-kb SRAM.

Reliability effects on MOS transistors due to hot-carrier injection

The high drain-effect transistor characteristic observed after hot-carrier injection and trapping in the oxide has been found to be due to the uneven trapped-carrier distribution near the drain, which causes the threshold voltage to vary as a function of drain voltage. A discussion of the role and effects of both electron and hole injection is presented. The nonlinear distribution of carriers trapped in the gate oxide is described. One result is that the nonuniform surface band bending causes the subthreshold leakage to be an exponential function of the drain voltage. The combined increase in threshold voltage, subthreshold leakage, and a decrease in subthreshold slope will translate into slower circuit speed and higher standby power dissipation [37] in CMOS circuits. An experimental model of the mean time to failure, for NMOS devices fabricated with two different source-drain diffusions, is also presented. For the first time, the model has been extended to include the channel-length dependence. The model assumes a reliability criterion of less than a 10-mV threshold-voltage shift in 100 000 h of operation. Experimental results and subsequent calculations show that for 350-Å gate-oxide devices at 5.0 V operation, 2.5 µm is the minimum electrical channel-length device which can be fabricated using a traditional source-drain process. Conversely, submicrometer electrical channel-length devices can be fabricated using an arsenic-phosphorous "graded" source-drain process, even at 5.5-V operation.

Reliability Effects on MOS Transistors Due to Hot-Carrier Injection

The high drain-effect transistor characteristic observed after hot-carrier injection and trapping in the oxide has been found to be due to the uneven trapped-carrier distribution near the drain, which causes the threshold voltage to vary as a function of drain voltage. A discussion of the role and effects of both electron and hole injection is presented. The nonlinear distribution of carriers trapped in the gate oxide is described. One result is that the nonuniform surface band bending causes the subthreshold leakage to be an exponential function of the drain voltage. The combined increase in threshold voltage, subthreshold leakage, and a decrease in subthreshold slope will translate into slower circuit speed and higher standby power dissipation [37] in CMOS circuits. An experimental model of the mean time to failure, for NMOS devices fabricated with two different source-drain diffusions, is also presented. For the first time, the model has been extended to include the channel-length dependence. The model assumes a reliability criterion of less than a 10-mV threshold-voltage shift in 100 000 h of operation. Experimental results and subsequent calculations show that for 350-/spl Aring/ gate-oxide devices at 5.0 V operation, 2.5 /spl mu/m is the minimum electrical channel-length device which can be fabricated using a traditional source-drain process. Conversely, submicrometer electrical channel-length devices can be fabricated using an arsenic-phosphorous graded source-drain process, even at 5.5-V operation.

A high performance 1 Mbit EPROM

A high-performance 1-Mb EPROM has been developed by utilizing advanced 1.2-/spl mu/m minimum design rule technology. The device technology used is n-channel E/D MOS. The memory cell size is 5.5/spl times/7.5 /spl mu/m and the die size is 9.4/spl times/7.2 mm. The word organization is changeable between 64K words/spl times/16 bits and 128K words/spl times/8 bits. The active power dissipation is 500 mW and the standby power dissipation is 150 mW. The access time is typically 200 ns. The programming voltage is 12-14 V and the programming pulse width is typically 1 ms/word. In order to realize such a high-density, high-speed, low power 1-Mb EPROM, 1.2-/spl mu/m minimum patterning process technology, a high-speed sense amplifier, and a high-speed decoder are used.

Novel adaptive biasing amplifier

A novel adaptive biasing amplifier is presented. This amplifier with a very low standby power dissipation has a high driving capability and consumes less power than the previously presented adaptive biasing amplifiers.

A 35 ns 16K NMOS static RAM

An NMOS 16K/spl times/1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 /spl mu/m gate length transistor, high speed sense amplifier, and reduction on delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of the poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.

Adaptive biasing CMOS amplifiers

Two transconductance amplifiers are presented in which the concept of an input dependent bias current has been introduced. As a result, these amplifiers combine a very low standby power dissipation with a high driving capability. The first amplifier, suited for SC filters, is fairly small (0.075 mm/SUP 2/) and has a slew rate which is more than an order of magnitude better than micropower amplifiers presented earlier. The second amplifier can be used as a micropower buffer. Nearly the whole supply current is used to charge the load capacitor so that this amplifier has a high efficiency.

An 18 ns CMOS/SOS 4K static RAM

A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.

The punchthrough device as a passive exponential load in fast static bipolar RAM cells

It is shown that the punchthrough device can be used as a passive exponential load in fast static bipolar RAM cells. The advantages are that the cell standby/read current ratio can be very large (> four decades), and that the cell area can be very small due to the fact that the punchthrough load is a vertical device. In this cell, a very small standby power dissipation(<0.1 /spl mu/W) is combined with a short access time (<10 ns). A static noise margin calculation for the cell is included. The general standby/read switching behaviour of memory cells with exponential loads is explained. The cell sensitivity to /spl alpha/-particles is discussed.

A charge-pumping-loop concept for static MOS/RAM cells

A novel bistability concept based on a charge-pumping loop is presented. The loop consists of a charge pump and a simple two-device inverter. With an additional select transistor, the loop can be used as a static MOS/RAM cell. The proposed cell configurations are realized with only four devices, one or two shared supply lines, and an address-bit line pair. Feedback is accomplished with a single non-cross-coupled path. These cells can be manufactured with any industry-standard technology in a considerably smaller silicon area in comparison with the conventional flip-flop configuration. The standby power-dissipation level of the cells is also sufficiently low to meet the objectives of the high-density RAM design.

A 1Kx8-bit 5 V-only static RAM

Describes an 8K static RAM with 300 ns access time. The device is organized as a 1K/spl times/8 with a single 5 V power supply. Clocked peripheral circuitry with high value sustaining resistors allows low standby and active power dissipation and infinite chip select length. Process and design considerations are discussed, as well as internal chip timing and circuit schematics.

A CMOS/SOS 4K static RAM

Discusses high density CMOS/SOS technology used to develop a fully static 4096-bit RAM with a five-transistor storage cell. Selection of a five-transistor memory cell has reduced the access to the flip-flop storage element to a single word line transistor and bit line. The word line transistor must be able to prevent data altering currents from entering the memory cell at all times except for the write operation. The write operation is enhanced by reducing the bias voltage across the memory cell, thereby making the current needed to alter the cell smaller. Through the use of a 5 /spl mu/m design rule, the memory cell occupies 2913 /spl mu/m/SUP 2/. The 4096-bit static CMOS/SOS RAM contains 22553 transistors in 20 mm/SUP 2/. Organised as 1024 4-bit words, the RAM has a read cycle time of 350 ns and standby power dissipation of 50 /spl mu/W at V/SUB cc/=5 V and temperature of 27/spl deg/C.

Radiation Hardened 64-BIT CMOS/SOS RAM

Radiation hardening procedures have been implemented in design, analysis and fabrication of a 64-bit CMOS/SOS RAM. The resultant circuit is a moderately complex (714 transistor), dielectrically isolated integrated circuit which features high performance and high radiation tolerance. Typical electrical parameters include 120 nsec read-access time and 1?watt/bit standby power dissipation. The SOS construction minimizes radiation-induced transient photocurrents while a hardened gate insulator provides immunity to total dose effects. Transient radiation upset levels exceed 3 × 1010 rads(Si)/sec for short (? 50 ns) pulses and ionizing dose hardness exceeds 106 rads(Si). A neutron fluence of 3.65 × 1014 n/cm2 had no effect on circuit operation beyond that expected from the ionizing radiation alone.

Thin films on gallium arsenide

With the recent developments in the technology of gallium arsenide, it is likely that a greater use of this semiconductor material will emerge than at present. An important reason for this is the new understanding of ohmic-contact formation by a thin-film epitaxy process, which could possibly even find other wider applications in device manufacture now, and lead to the manufacture of normally-off m.o.s.f.e.t.s. The latter device is particularly suitable for high-speed integration and monolithic interfacing with optical devices because of its small standby power dissipation

A pulse-duration-stabilized complementary monostable†

Abstract The closely controlled mutual characteristics of modern low-cost planar transistors permit the design of a novel complementary monostable circuit which has zero standby power dissipation, a predictable pulse duration and which is suitable for use with single power supply logic systems such as transistor-transistor logic (T3L).