Transistor Stages Research Articles

Analog CMOS Design in Nanometer Regime

There is no doubt that the short-channel effects have affected the analysis and design of modern analog CMOS integrated circuits significantly. Thus, models that take into account these effects must be adopted in order to obtain more accurate results. In this paper, the AC small-signal low-frequency equivalent circuit of the short-channel MOSFET transistor is developed using an appropriate model. The impact of short-channel effects on the operation of basic building blocks of analog integrated circuits such as basic amplifier configurations, cascode stage, differential amplifier and composite transistor is investigated quantitatively. Additionally, the nonlinear distortion is investigated using the adopted model.

A monolithic gallium nitride‐based two‐phase synchronous buck converter with high operating frequency

AbstractThe need for a high‐frequency and high‐efficiency gallium nitride (GaN)‐based buck converter that can be controlled directly by a low swing pulse width‐modulated (PWM) signal, without the need for additional buffers or preamplifiers, poses a significant challenge in the field of power conversion and dynamically power supply applications. To solve this problem, this letter presents a monolithic two‐phase synchronous buck converter, fabricated using a 0.25‐um GaN‐on‐Si process, integrated both the drivers and power stage transistors, without requiring additional buffers or preamplifiers. So, the proposed converter can be directly controlled by a PWM signal with a swing of only 1 V (−0.5 to 0.5 V). At a 100‐MHz switching frequency, the converter achieves a maximum output power of 12 W with a power stage efficiency of 82%. The converter includes two identical half‐bridge Monolithic Microwave Integrated Circuit (MMICs), and with the frequency multiplication property of multi‐phase topology, the equivalent switching frequency can reach 200 MHz in the open‐loop operating mode. The experimental results show that the converter can track a 40‐MHz bandwidth envelope signal (256 QAM, 6 dB PAPR) with 80.1% efficiency.

A 7–13 GHz 10 W High-Efficiency MMIC Power Amplifier in 0.25 µm GaN HEMT Process

With the increase in applications of the millimeter wave spectrum for phased array radar systems, mobile 7–13 communication systems, and satellite systems, the demand for a wideband, high-efficiency, high-power monolithic microwave integrated circuit (MMIC) power amplifier (PA) is increasing. In this paper, a 7–13 GHz 10 W high-efficiency MMIC PA is designed. This amplifier consists of a two-stage circuit structure with two high electron mobility transistor (HEMT) cells for the driver stage and four HEMT cells for the power stage. To ensure high efficiency and a certain output power (Pout), both the driver–stage and power–stage transistors use a deep Class–AB bias. At the same time, in order to further improve the efficiency, low-loss and second–harmonic tuning techniques are used in the output and inter-stage matching networks, respectively. Finally, the electromagnetic simulation results show that within a frequency of 7–13 GHz, the amplifier achieves an average saturated continuous wave (CW) Pout of 40 dBm, a small signal gain of 14.5–15.5 dB, a power-added efficiency (PAE) of 30–46%, and the input and output return loss are better than 5 dB and 8 dB, respectively.

Efficiency Enhancement of CMOS Power Amplifier for RF Applications

This paper presented a new structure for the CMOS power amplifiers as a more effective trend to amplify radio frequency (RF) signals compared to polar power amplifiers PA's by using envelope removal and restoration (EER) technique. Polar PA offers high-efficiency RF-modulated linear signal amplification. However, these amplifiers need high uniformity between the amplitude and phase of the modulated signals. The last translates promptly into higher energy consumption. Rather than deconstructing the quadrature signals into the combination of phase and amplitude signals, it is suggested that the CMOS quadrature power amplifier (QPA's) technique had been used to amplify RF signals immediately. The linearity, bandwidth, efficiency, and power consumption of the QPA's has been improved by separate amplitude and phase quadrature signals. The quadratic geometry architecture contains two bridges from modulated PA's that are able to treat negative or positive voltages, modulation, and RF-power bundling. The design of the new structure is compared with respect to parameters such as fundamental frequency, power gain, PAE, output power, technology or fabrication process, and number of stage transistors. Simulation results for PA's design using CMOS process show an effective quadrature model by a power-added-efficiency (PAE) of 78.413% at a maximum output power of 21.619dBm. The third intermodulation IDM3 is -49.2dBc at output power driven at frequency 2.4 GHz and input power greater than 20dBm. The amplitude and phase distortion has been obtained of 1.4 and 0.26 ᵒ/dB respectively at 50MHz of bandwidth for modulated signals.

SOUND CONTROL HOME AUTOMATION

This is a sound control home automation project that uses sound to turn on or off any electrical circuit. This is a circuit that works by creating sound from a distance. When a person claps or makes a sound that can be caught by a condenser microphone, the circuit's output light turns on. If another person claps, the light will turn off. The basic idea behind this project is that the condenser microphone catches up your claps, coughs, and the sound of a book being knocked off the table. It generates a weak electrical signal that is amplified by the transistor stage that follows. Each signal changes the state of two transistors coupled in a bistable multivibrator. One of these transistors controls a bulb through a heavier transistor. This is a sound-activated switch. Sound, for example, may be used to turn on or off a fan, a fluorescent light, a television, and other equipment.

Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs

This paper presents an optimization methodology for inductorless noise-cancelling CMOS Low-Noise Amplifiers (LNA), whose performance typically depends on a tight balance in the design of two transistor stages. Due to the different functions of the two parts, noise-cancelling amplifiers become very difficult to analyze in detail by closed-form expressions or straight simulations: each section significantly affects the results of the other. In addition, opposed specifications, such as gain and cut-off frequency, suppose another grade of complexity due to the interplay of the two branches of the circuit. As a solution, the proposed methodology uses a visualization of the design window in 2-dimensional space to optimize the different parameters of the specifications without compromising the others. All specification constraints are represented in a single figure instead of one graph per parameter. Compared with most optimization methods, the design window methodology observes the design span instead of isolated design points that might not guarantee feasibility. Furthermore, as a simulation-driven exploration method, it benefits from complete device models with high-order effects that would be too complex to include in analytical expressions but critical to achieving maximum efficiency. As an example of the method, the paper describes the optimization of the well-known CS-CG noise-cancelling LNA in 65-nm standard CMOS technology. Final post-layout simulations report very competitive results with a 3.7-dB noise figure, a 17-dB gain, and a cut-off frequency above 7 GHz.

Surrogate based design optimization of low noise amplifier for ISM band

Design optimization of microwave circuits is a crucial matter for microwave engineers. For the last decades, researchers had been studying surrogate models for a computationally efficient design optimization process. Artificial Intelligence based algorithms had been used for modelling of complex microwave stages such as antenna, amplifiers and frequency selective surfaces. In this study, design optimization of a Low Noise Amplifier (LNA) based on surrogate models for both transistor stage and input & output matching circuits had been presented. Support Vector Regression Machine had been used for creating surrogate models of a microwave transistor and a non-uniform transmission line for having a fast and accurate LNA design optimization process alongside a low profile and high performance LNA using on-uniform transmission lines. By using this methodology, not only designer can create a mapping for missing points in the sparse sample S parameter data points provided by manufacturers but also the overall simulation duration can be significantly reduced thanks to the fast nature of surrogates compared to EM simulators. Here, the proposed surrogate models had been used alongside of Particle Swarm Optimization algorithm to determine optimal geometrical values of input/output matching networks. Then the obtained designs are prototyped and measured. The measured results are also compared with the performance results of counterpart design in literature. As for results, not only the proposed methodology is an effective, fast and reliable method for computationally efficient design optimization process of LNA but also provides better results than the counterpart design in literature.

Метод снижения потерь энергии в импульсном преобразователе напряжения

A signal timing calculation method to control power switches of bidirectional switching converter (SC) with high efficiency is proposed. The method is applicable for MOSFET-based cascaded boost-buck converter, which has a negative offset current flow at the beginning of each conversion period. This current allows to perform turning on switches under zerovoltage and zero current switching condition to minimize switching losses. Meanwhile, the delay time between halfbridge transistors’ switching points is needed, when transistors’ output capacitances recharging takes place with following anti parallel body diode of transistor is being turned on unlocking. A proposed method is based on a switching delay time of input stage transistors valuation for the worst case of SC’s components’ parameters scatter, and provides guaranteed turning on of the upper transistor of the input stage under zero voltage and zero current condition. A clarified offset current calculation method is provided which introduces described time delays and SC’s input voltage.

A low power and jitter delay cell with pulse width modulation for wide range delay lock loops

To reach a delay lock loop (DLL) with low jitter and power for wide range frequency applications, the performance of delay cell used in the voltage-controlled delay line (VCDL) play the most important role. In recent years, a variety of methods have been proposed to achieve a wide-range delay cell. In this paper, a method is proposed in which pulse width modulation (PWM) technique is used to generate a wide-range delay it is in a better trade-off with power and jitter with respect to previous work. PWM circuit creates two control signal (rising and falling control signal) for last stage transistors. These control signals generate a signal that is similar to the input signal of the delay cell with a controllable delay. The proposed delay cell is able to generate a delay that is more than half of the input clock period leads to a wideband DLL. The delay cell has been simulated in TSMC RF CMOS 0.18 μm technology at 1.8 V supply voltage. The simulation results show that the desired structure has a delay range of 195 ps to 3.4 ns in a frequency range 300 MHz to 1 GHz. Moreover, its RMS jitter is equal to 2–22 ps, 0.33 ps at 300 MHz and 1 GHz, respectively.

The outlook for multivibrator application in the present day electronic systems

The paper discusses challenges that the present-day electronic industry of the Russian Federation faces today, analyses reasons for lagging in this sector in volume and production scale of the finished products in comparison to the leading in this area countries, suggests ways for reaching a new level in this industry by implementing a nationwide digitalization, reviews a place of digital signals in modern-day electronic, their types, creation methods, main characteristics, devices for generation and processing. The method of digital signals forming using the multivibrator was suggested in this paper. Different multivibrator types were reviewed, including the multivibrator with AND-NOT gates, its advantages were considered in comparison with the transistor stage multivibrators, parameters of the electronic circuit elements in the AND-NOT gate multivibrator for generating a signal with the required characteristics were calculated, then the multivibrator was assembled and the output signal parameters were taken down. The output signal parameters and the calculated parameters were identical. The conclusion was made about the possibility of the suggested AND-NOT gate multivibrator application in the complex automatic control circuits and electronic systems indication circuits as a device that generates signals with the required parameters.

The design of a vehicle detector and counter system using inductive loop technology

Abstract Scheduling vehicles at multiple intersections remain an issue of concern in road traffic control. Traffic lights have been widely employed in many countries, however, determining the best intersection to grant access to using the number of vehicles present as a yardstick needs to be improved on. Therefore, this article presents the design of a vehicle detector and counter system using inductive loop technology. The proposed system is majorly made up of the inductive loop section, the electronic vehicle detector section and the counter section. The inductive loop uses an electromagnetic communication to create an electric current in a nearby wire, when a vehicle crosses the loop, the inductance of the loop is increased. Based on the oscillating signal received from the inductor loop, the electronic detector section uses a voltage comparator stage and Darlington transistor arrangement to detect the vehicles on the queue. Afterwards, two up-counters and an up/down counter were used to keep track of vehicles entering and leaving the queue. The design was simulated and tested in Proteus virtual system modelling software. The simulation results obtained revealed that the design could be employed for detecting and counting vehicles at intersections so as to effectively control traffic.

Balanced to Unbalanced: An Overview of Multifunctional Wideband Balanced-to-Unbalanced Four- and Five-Port Filtering Power Dividers

Fifth-generation (5G) communication techniques are growing in popularity, and 5G will become the commercial operation standard for mainland China in 2020 [1]. As the next-generation mobile communication network, 5G will not only greatly improve communication efficiency; it will also change the way people live and work. The 5G communication system contains the millimeter-wave and sub-6-GHz bands. For the sub-6-GHz band, circuits are becoming ever more compact and multifunction; thus, electromagnetic interference and multicoupling problems will greatly affect the entire system's performance [2]-[4]. In response, balanced circuits with higher immunity to environmental noises [5]-[8], lower electromagnetic interference [9]-[11], and better dynamic range [12]-[15] have attracted increasing attention in the past few years, and a large number of balanced circuits are being conceived [16], [17]. Currently, all feature differential-mode input and output terminals, so they cannot be connected directly to single-ended circuits. Balanced filters, antennas, and power dividers that can be cointegrated with balanced active circuits are required for the development of fully balanced transmitter and receiver RF chains, such as the balanced power dividers that can be connected to a Doherty power amplifier in a balanced system. In this case, balancing is only necessary at the input and output stages. It is expected that the transistor stage is still a single-ended structure, where only two amplifier devices are needed [18].

Global Design of a Waveguide X-Band Power Amplifier

The design and the fully coupled Thermodynamic and Structural Mechanics simulation of a Spatial Power Amplifier are described in this paper. The amplifier is realized in a WR90 waveguide, employing Fin-Line Transitions and Monolithic Microwave Integrated Circuit Solid State Power Amplifiers. Global performances of active devices and combining structure have a critical dependence to the thermo-mechanical condition of operation. The temperature alterations and thermal expansions, related to the power dissipation of the devices, have been analyzed in order to lead the amplifier at extreme power output, avoiding malfunctions. The proposed analysis accounts for the effects of different distributions of heat flux and stresses as a consequence of the different power consumption of the Driver and Final stage transistors. The amplifier combines 16 active devices of 7.9 W maximum power output with a power dissipation of 20 W, heating the transistor channel to140° and deforming the mechanical structure to 4.9µm with a maximum stress of 0.41 GN/m2. A maximum power output of 112W with a Return Loss greater than 12 dB in the whole X-Band is ensured

PCB-Embedded GaN-on-Si Half-Bridge and Driver ICs With On-Package Gate and DC-Link Capacitors

A low-inductive half-bridge and gate driver package with on-package gate and dc-link capacitors is realized by printed circuit board (PCB) embedding of two GaN-on-Si ICs. While monolithic half-bridge and driver integration reduces on-chip parasitics, it does not solve the interconnection challenge to external capacitors. This letter solves this issue through advantageous combination of PCB embedding and monolithic circuit integration. This letter uses GaN-on-Si power circuits with integrated gate drivers, freewheeling diodes, and temperature and current sensors. GaN ICs are fabricated with thick copper on both sides, which makes them applicable to commercial PCB-embedding technologies. Thermal aspects are discussed and electromagnetic simulations used to compare the PCB-embedded package to a bond wire based package. A PCB-embedded dc–dc converter is operated up to 350 V and 450 W with up to 98.7% efficiency. 380 V hard-switching transitions show below 8% over- and undershoot despite over 120 V/ns slew rates. Parallel platelike placement of silicon flip-chip capacitors above the gate driver final stage transistors and separated only by a thin PCB layer increased the gate-loop parasitic inductance by only 40 pH.

94 GHz eight-way power amplifier with high output power and power-added efficiency in 90 nm CMOS

A four-stage eight-way CMOS power amplifier (PA) for 94 GHz radar sensor is reported. The PA constitutes a common-source (CS) input stage, a CS first gain stage, a two-way CS second gain stage, followed by an eight-way CS output stage using miniature triple Y-shaped divider and combiner. Broadband π-match input, inter-stage, and output networks are adopted for broadband impedance or power matching. Inductive shunt-shunt feedback technique is used at the input and the first gain stages to boost gain. This leads to a boosted saturated output power (Psat) and power-added efficiency (PAE). At every division’s input (i.e. the drain of the parallel CS output stage), the triple Y-shaped current combiner transforms the serial RL load into the optimum load impedance (homologous to the optimum Psat and PAE) of the output stage transistors. At supply voltage (VDD) of 1.2 V, the PA attains Psat of 12.1 dBm, gain of 17.5 dB, and PAE of 14.8% at 94 GHz, the best values ever demonstrated for a W-band CMOS PA in 90 nm CMOS. Moreover, at high VDD of 2.4 V, the PA achieves high Psat of 18.2 dBm, gain of 19.6 dB, and PAE of 15% at 94 GHz. The eminent results of the CMOS PA reveal that it is hopeful for 94 GHz radar sensor.

Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier

A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and a slew-rate enhanced linear amplifier (LA) are presented. In addition to smaller ripple and lower losses of 3L-SWCs, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80 MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage $V_{\mathrm{ CF}}$ and eliminates the conventionally required calibration loop to control it. The hysteretic-controlled 3L-SWC provides a high percentage of power amplifier (PA) supply load current with lower ripple, reducing the LA high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the LA, resulting in slew rate of over 307 V/ $\mu \text{s}$ and bandwidth of over 275 MHz for the LA. The SRE circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of output without modifying the operating point of the remaining LA, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in a 65-nm CMOS process. The measurement results show the tracking of long-term evolution (LTE)-40-MHz envelope with 93% peak efficiency at 1-W output power, while the SRE is disabled. Enabling the SRE, it can track LTE-80-MHz envelope with peak efficiency of 91%.

Single JFET Front-End Amplifier for Low Frequency Noise Measurements with Cross Correlation-Based Gain Calibration

We propose an open loop voltage amplifier topology based on a single JFET front-end for the realization of very low noise voltage amplifiers to be used in the field of low frequency noise measurements. With respect to amplifiers based on differential input stages, a single transistor stage has, among others, the advantage of a lower background noise. Unfortunately, an open loop approach, while simplifying the realization, has the disadvantage that because of the dispersions in the characteristics of the active device, it cannot ensure that a well-defined gain be obtained by design. To address this issue, we propose to add two simple operational amplifier-based auxiliary amplifiers with known gain as part of the measurement chain and employ cross correlation for the calibration of the gain of the main amplifier. With proper data elaboration, gain calibration and actual measurements can be carried out at the same time. By using the approach we propose, we have been able to design a low noise amplifier relying on a simplified hardware and with background noise as low as 6 nV/√Hz at 200 mHz, 1.7 nV/√Hz at 1 Hz, 0.7 nV/√Hz at 10 Hz, and less than 0.6 nV/√Hz at frequencies above 100 Hz.

A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability

In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 $\mu \text{W}$ and quiescent current of 26 $\mu \text{A}$ . It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.

W-Band power amplifier with high output power and power-added efficiency in 90 nm CMOS

This paper reports a three-stage four-way power amplifier for 94 GHz image radar systems in 90 nm CMOS technology. The PA comprises a common-source (CS) input stage and a CS gain stage with wideband π-match input, inter-stage and output networks, followed by a four-way CS output stage using miniature dual-Y divider and combiner. Inductive shunt–shunt feedback technique is used at both the input and gain stages to enhance gain, which in turn leads to a higher output power (Pout) and power-added efficiency (PAE). At each branch’s input terminal (i.e. the drain terminal of the parallel CS output stage), the dual-Y current combiner can convert the serial RL load to the optimal load impedance (corresponds to the optimal Pout and PAE) of the output stage transistors. At 94 GHz, the PA achieves power gain of 16.5 dB, Pout of 16.5 dBm, and PAE of 18.3%, one of the best results ever reported for a W-band PA in 90 nm CMOS. The excellent performance of the CMOS PA indicates that it is suitable for 94 GHz image radar transceivers.

Design of low-voltage shallow-depth differential source coupled logic using feedback and feedforward techniques

A shallow-depth differential source coupled logic is proposed in this paper, targeting low-voltage high-speed applications. In this logic, the number of transistor stages decreases from supply voltage to ground. This feature offers performance advantage over DCVSL (Differential Cascode Voltage Switch Logic) and DSCL (Differential Static CMOS Logic) styles in a circuit block. Using 180 and 65-nm standard CMOS technologies, the proposed logic demonstrates an average speed-up of 30% over CVSL (Cascode Voltage Switch Logic) based structures in the low-voltage region due to fewer series stages between supply voltage and ground nodes with near EDP (Energy-Delay Product) to its DSCL counterpart. Simulation and post-layout simulation results of 8-bit carry chain generator show that the proposed logic is 31, 23 and 13% faster than the DCVSL, DSCL and MTCML (Multiple-Tailed CML) carry generator chain, respectively. Proposed logic also demonstrates 7% and 6% PDP (power-delay product) reduction than DCVSL and DSCL carry generator chain, respectively.