Abstract
A low-inductive half-bridge and gate driver package with on-package gate and dc-link capacitors is realized by printed circuit board (PCB) embedding of two GaN-on-Si ICs. While monolithic half-bridge and driver integration reduces on-chip parasitics, it does not solve the interconnection challenge to external capacitors. This letter solves this issue through advantageous combination of PCB embedding and monolithic circuit integration. This letter uses GaN-on-Si power circuits with integrated gate drivers, freewheeling diodes, and temperature and current sensors. GaN ICs are fabricated with thick copper on both sides, which makes them applicable to commercial PCB-embedding technologies. Thermal aspects are discussed and electromagnetic simulations used to compare the PCB-embedded package to a bond wire based package. A PCB-embedded dc–dc converter is operated up to 350 V and 450 W with up to 98.7% efficiency. 380 V hard-switching transitions show below 8% over- and undershoot despite over 120 V/ns slew rates. Parallel platelike placement of silicon flip-chip capacitors above the gate driver final stage transistors and separated only by a thin PCB layer increased the gate-loop parasitic inductance by only 40 pH.
Highlights
M ONOLITHIC integration of circuits and sensors [1]– [5] in the lateral GaN-on-Si technology increases the Manuscript received May 11, 2020; revised June 6, 2020; accepted June 21, 2020
There are still critical external interconnections required for the operation of monolithic power ICs in converters: The gate driver requires interconnection to external gate supply capacitors
While the dielectric strength of the NCA layer itself is initially sufficient as high-voltage isolation [18], further possible failures of printed circuit board (PCB)-embedded packages from resin densification [18], humidity, or delamination [19] should be further studied
Summary
M ONOLITHIC integration of circuits and sensors [1]– [5] in the lateral GaN-on-Si technology increases the Manuscript received May 11, 2020; revised June 6, 2020; accepted June 21, 2020. Color versions of one or more of the figures in this article are available online at https://ieeexplore.ieee.org. The half-bridge power path requires interconnection to external dc-link capacitors In both cases, the parasitic inductance of this external interconnections will limit the switching performance [9]. The parasitic inductance of this external interconnections will limit the switching performance [9] To address this challenge, this letter uses printed circuit board (PCB)embedding technology to package two GaN ICs in a half-bridge package with on-package bypass capacitors. This letter uses printed circuit board (PCB)embedding technology to package two GaN ICs in a half-bridge package with on-package bypass capacitors This combination of monolithic circuit integration, package-level integration, and on-package capacitors simultaneously enables high functionality and low parasitic inductance.
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