Multiplier Stages Research Articles

The Plasmodium falciparum histone methyltransferase SET10 participates in a chromatin modulation network crucial for intraerythrocytic development.

The lifecycle progression of the malaria parasite Plasmodium falciparum requires precise tuning of gene expression including histone methylation. The histone methyltransferase PfSET10 was previously described as an H3K4 methyltransferase involved in var gene regulation, making it a prominent antimalarial target. In this study, we investigated the role of PfSET10 in the blood stages of P. falciparum in more detail, using tagged PfSET10-knockout (KO) and -knockdown (KD) lines. We demonstrate a nuclear localization of PfSET10 with peak protein levels in schizonts. PfSET10 deficiency reduces intraerythrocytic growth but has no effect on gametocyte commitment and maturation. Screening of the PfSET10-KO line for histone methylation variations reveals that lack of PfSET10 renders the parasites unable to mark H3K18me1, while no reduction in the H3K4 methylation status could be observed. Comparative transcriptomic profiling of PfSET10-KO schizonts shows an upregulation of transcripts particularly encoding proteins linked to red blood cell remodeling and antigenic variation, suggesting a repressive function of the histone methylation mark. TurboID coupled with mass spectrometry further highlights an extensive nuclear PfSET10 interaction network with roles in transcriptional regulation and mRNA processing, DNA replication and repair, and chromatin remodeling. The main interactors of PfSET10 include ApiAP2 transcription factors, epigenetic regulators like PfHDAC1, chromatin modulators like PfMORC and PfISWI, mediators of RNA polymerase II, and DNA replication licensing factors. The combined data pinpoint PfSET10 as a histone methyltransferase essential for H3K18 methylation that regulates nucleic acid metabolic processes in the P. falciparum blood stages as part of a comprehensive chromatin modulation network.IMPORTANCEThe fine-tuned regulation of DNA replication and transcription is particularly crucial for the rapidly multiplying blood stages of malaria parasites and proteins involved in these processes represent important drug targets. This study demonstrates that contrary to previous reports the histone methyltransferase PfSET10 of the malaria parasite Plasmodium falciparum promotes the methylation of histone 3 at lysine K18, a histone mark to date not well understood. Deficiency of PfSET10 due to genetic knockout affects genes involved in intraerythrocytic development. Furthermore, in the nuclei of blood-stage parasites, PfSET10 interacts with various protein complexes crucial for DNA replication, remodeling, and repair, as well as for transcriptional regulation and mRNA processing. In summary, this study highlights PfSET10 as a methyltransferase affecting H3K18 methylation with critical functions in chromatin maintenance during the development of P. falciparum in red blood cells.

A V-band injection locking tripler with 26.8% locking range and 7.3-dBm output power in 65 nm CMOS

With a 65-nm CMOS process, a V-band wideband injection locking (IL) frequency tripler is proposed by cascading a multiplier and a driver amplifier stage. Concerning high output power and efficiency performance over a wideband locking range (LR), two transformer-based IL topologies are analyzed in the multiplier and driver stages, in which the cross-coupled pair is connected at the input and output ports of the transformer, respectively. Moreover, the active device is carefully designed in terms of the operating point of the harmonic generator and device sizing in the driver amplifier stage. With measurements, the proposed tripler achieves a maximum measured output power of 7.3 dBm with 22.4% output-to-DC power efficiency and 26.8% LR from 50.4 to 66 GHz. Including the output driver amplifier, the IL tripler consumes 24 mW DC power. The measured fundamental and 2nd-harmonic rejection ratios (HRR) are both better than 30 dBc, while the measured phase noise (PN) degradation is in close agreement with the theoretical value.

An optimized design of delay-and energy-efficient Booth multiplier

Multipliers are essential computation units in virtually all computing systems, including processors and numerous AI accelerator architectures. This paper presents an optimized architecture for a Booth multiplier, targeting high performance while minimizing energy consumption and area utilization. The design optimization focuses on all three multiplier stages: partial product generation, reduction, and summation. To enhance delay and energy efficiency in the partial product generation stage, we first employed a simplified configuration comprising inverters and a sign selection unit instead of complex binary-to-two's complement circuitry. Next, to achieve further delay and area efficiency at this stage, logic optimization is applied at the partial product's generation circuitry by designing Booth encoders to remove redundant logic in multiplexers circuitry. Moreover, we introduced specialized sign compressors tailored for carry-save compression in the compression stage. Compared to conventional counterparts, these compressors offered lower power consumption and reduced critical path delay with only two XOR logic gates. Finally, in the summation stage, we proposed an optimized design segment for Carry Look-Ahead Adder for the final summation stage, designed to deliver swift throughput with minimal fan-in logic gates, even in the context of high bit-width configurations. This segment is cascaded to make a 13-bit final adder for the summation stage in the proposed design. The proposed architecture undergoes ASIC-targeted synthesis in Cadence Genus employing FreePDK CMOS 45 nm process technology. Synthesized results, along with theoretical design complexity comparison, demonstrate that the proposed design surpasses state-of-the-art 8 × 8 multiplier designs by critical metrics, including delay, power consumption, area utilization, power delay product, and area delay product.

Design and analysis of an interleaved step-up DC–DC converter with enhanced characteristics

In this paper, an interleaved DC–DC step-up converter with improved characteristics based on a voltage multiplier rectifier is presented. The proposed converter is presented and analyzed for two different operating duty regions including operating region 1 (0 < D ≤ 0.5), and operating region 2 (0.5 ≤ D < 1). This converter can be used in various applications such as energy storage, electric vehicles, and renewable energy systems. This converter is composed of two stages: an interleaved boost stage and a voltage multiplier rectifier stage, which collectively forms its general structure. The interleaved boost stage is a type of two-phase boost converter that transforms the input DC voltage into a high-frequency AC square waveform. This waveform can be readily filtered using smaller capacitors. The square-shaped voltage waveform from the interleaved boost stage is rectified and converted to a high DC voltage by the Voltage Multiplier Rectifier (VMR) stage. The operating regions, the evaluation of the steady-state condition, the voltage gain of the proposed converter's parasitic and ideal models as well as its losses and efficiency analysis have been evaluated. The proposed converter has an efficiency of 97% at the output power of 150 W. The proposed converter is simulated to convert a voltage of 25–159.5 V and to validate the mathematical relationships and simulation results, a laboratory prototype has been developed. The simulation and experimental results show the precision of the performance of the proposed interleaved boost converter.

A single switch high gain multilevel boost converter with switched inductor topology for photovoltaic applications

This paper proposes a new transformer-less single-switch high-gain dc-dc converter for solar power systems. The suggested converter is created by supplementing the conventional boost converter with a switched inductor cell plus a voltage multiplier stage. The converter has several benefits, including a high voltage conversion ratio, reduced voltage stress on semiconducting switches and diodes, a reduction in the need for gate drivers because only one switch is used, as well as constant input current to prolong the lifespan of the photovoltaic cell. The analytical waveforms of the recommended converter can be seen in the continuous conduction mode (CCM). The analysis of voltage stress is done. In the presence of parasitic components, increased voltage gain and efficiency were also obtained.The proposed high-gain converter topology is compared to recently published high-gain converter topologies in terms of performance. Using PSIM, a high-gain dc-dc converter's performance is studied and analysed with regard to its low switching voltage stress. The suggested converter is successful in stepping up 20V to 400V at 160W power capacity, while offering a continuous input source current at 95% efficiency.

In-air experimental achievement of high-voltage DC power supply to be installed in a tandem electrostatic accelerator system for boron neutron capture therapy application.

The boron neutron capture therapy (BNCT) system developed by the Korea Institute of Radiological and Medical Sciences is a compact neutron source that can be installed at medical institutes. The target energy was accelerated to a maximum of 2.4 MeV-20 mA by introducing a gas stripping device that converts negative hydrogen ions into positive ions. By using the tandem-type accelerator in this way, a high-voltage DC power supply was designed with 1.2 MV-45 mA as the maximum capability. The design was improved to reduce the number of stages of a Cockcroft-Walton voltage multiplier. Hence, the ripple risk of the DC flat top resulting from unwanted stray capacitance was lowered. The overall height and volume of the Cockcroft-Walton voltage multiplier were reduced to less than half those of the existing design method, making miniaturization possible. After such advanced design and manufacturing, performance tests were performed at 750 kV-45 mA under 23 stages of the Cockcroft-Walton voltage multiplier, which is the highest level that can perform at its maximum under in-air conditions. It demonstrated stable performance under in-air conditions without breakdown for 2h, even at 620 kV-35 mA. To reach the final target of 1.2 MV-45 mA, the groundwork is laid for achieving experimental performance while satisfying the optimal requirements in SF6 gas.

A fast simulation model of 2-D photoelectron track images for gaseous X-ray polarimetry

Gaseous polarimetry applies in soft X-ray polarization detection, typically like the Gas Pixel detector (GPD) and the micropattern time projection chamber (TPC). The polarization phase angles resolve from photoelectron track trajectories for both of them. The photoelectron track images derived from read-out pixels or strips are the key to determining the performance of the polarimetry. Gaseous X-ray polarimetry is regularly optimized and diagnosed by the Geant4 associated with Garfield++ and finite element analysis software (full simulation). Although the results are more realistic by the full simulation, the sample generation is low efficiency, especially for large gain values of the multiplier stage. The 2-D photoelectron track images regularly generate by a gaussian smear of initial ionization electrons at present. However, discrepancies exist in the modulation curves, resulting in fuzzy diagnoses and optimization of polarimetry. In this study, a fast simulation framework is constructed, the reconstruction of polarization phase angles and energy spectrum of the samples obtained from the fast simulation are consistent with those from experiments and the full simulation, and the deviation of modulation factor is within 2% for both situations of the GPD and TPC. In addition, the fast simulation greatly improves the sample generation efficiency. These results illustrate the fast simulation model is relative accuracy and high efficiency, which provides a useful tool for gaseous X-ray polarimetry.

Recreational trail development within different geographical contexts as a determinant of income multiplier and local economic impact

The development of recreational trails has gained popularity in recent years and therefore many scholars have studied various aspects of them. However, the recreational trail theoretical framework lacks an understanding of the relationship between the stage of trail development and income multiplier value. This research aims to examine this relationship and thus advance the traditional theory of recreational trail economic impact by providing an explanation of the relationship between the stage of trail development and the income multiplier. This study applied a combined approach of Recreation Opportunity Spectrum (ROS) to assess the stage of trail development and the Ad hoc model to estimate the income multiplier and economic impact. The results of this study reveal that there is a strong correlation between the stage of trail development and income multiplier and provide a novelty in traditional recreational trail management and economic impact theory thus enriching the topical literature.

DC‐DC parallel legs linked high gain converter for microgrid applications

AbstractFor microgrid operations, this article suggests a DC‐DC Parallel Legs Linked High Gain Converter. To realize high voltage gain, the recommended converter is transformer‐free and developed with n‐parallel legs. One active switch, one capacitor, one inductor, and one diode make up each leg of the boost converter. The operating principle, characteristic waveforms, and steady‐state study are provided for continuous and discontinuous conduction modes. High voltage gain, low voltage and low current stress on switches, compact size inductors, and low voltage capacitors are the important features of the recommended converter. The suggested converter achieves a large voltage gain without the demand of high‐frequency transformers or voltage multiplier stages. Furthermore, it works on two separate duty cycles, allowing for a wide variety of duty cycle functioning. The suggested converter is compared to a newly discussed converter, and the fundamentals of reactive component design and semiconductor device selection are discussed. The experimental findings are shown, demonstrating that the suggested converter's theoretical analysis and functioning are correct.

Highly extendable passive current balancing interleaved high step‐up boost converter using voltage multipliers

AbstractHigh step‐up boost converters with large input current capacity are necessary for low‐voltage renewable energy sources, such as photovoltaic panels and fuel cells. Interleaved converters are a suitable topology for low‐voltage, large input current applications. Conventional interleaved converters, however, face a variety of challenges, such as the necessity of additional current control loops for active current balancing, increased voltage stress of semiconductors, and poor extendibility. In this paper, highly extendable interleaved high step‐up boost converters with a passive current balancing and reduced semiconductor voltage stresses are proposed. Current capacities and step‐up conversion ratios of the proposed converters can be arbitrarily enhanced by extending the number of phases and voltage multiplier (VM) stages, respectively. The experimental results of 500‐W prototypes demonstrated passive current balancing, reduced semiconductor voltage stresses, and enhanced step‐up conversion ratios.

18S rRNA Gene-Based Piroplasmid PCR: An Assay for Rapid and Precise Molecular Screening of Theileria and Babesia Species in Animals.

PurposeThe parasites of genera such as Babesia and Theileria are called piroplasmids due to the pear-shaped morphology of the multiplying parasite stages in the blood of the vertebrate host. Because of the enormous number of parasite species and the challenges of multiplex PCR, initial screening of samples using piroplasmid-specific PCR may be a more cost-effective and efficient technique to identify parasite species, especially during epidemiological studies. Accordingly, 18S rRNA PCR was standardized and optimized on common piroplasmids of different animals like cattle, buffaloes, sheep, goats, dogs, horses, and leopards.MethodsBloods samples from 1250 animals were collected from different animals in Junagadh district of Gujarat, India. 18S rRNA PCR was standardized and optimized as a primary method for molecular screening of piroplasms in domestic and wild animals. The method was checked for its analytical sensitivity and specificity. Parasite species-specific PCR and sequencing was used to validate the test. Moreover, in-silico restriction enzyme (RE) analysis was also done to assess its applicability in PCR–RFLP.ResultsPiroplasm infections were recorded in 63.3% of animals in Junagadh. The 18S rRNA PCR detected the piroplasmid DNA in as low as 39 picograms (pg) of whole blood genomic DNA isolated from microscopically Theileria positive blood samples and no reactivity was recorded from common but unrelated haemoparasites viz., Trypanosoma evansi, Hepatozoon spp., Anaplasma spp., and Ehrlichia canis was observed. The 18S rRNA PCR assay findings were confirmed by species-specific PCR and sequencing. Analysis of different sequences generated using 18S rRNA PCR revealed that the amplicon size of Babesia spp. is nearly 400 bp (393–408 bp) whereas Theileria spp. were more than 400 bp (418–424 bp). The percentage of sequence divergence among Babesia and Theileria spp. was 7.3–12.2% and 0.7–12.2%, respectively. In-silico restriction enzyme (RE) analysis reveals the presence of at least one site for a commercially available RE in 18S rRNA fragments of every parasite, which can differentiate it from its congeners.ConclusionsThe presented universal oligonucleotide-based PCR assay provides a highly sensitive, specific, cost-effective, and rapid diagnostic tool for the initial screening of piroplasmids infecting domestic and wild animals and is potentially helpful for large-scale epidemiological studies.Supplementary InformationThe online version contains supplementary material available at 10.1007/s11686-022-00625-2.

Design of High speed Multiplier using Input Scrambled 5-3 compressor for Error Tolerant image processing

The imprecise multiplier has received a lot of attention for many high-performance systems used today such as in Image Processing, Microprocessors where multiplication is one of the fundamental operations. In order to shorten the reduction stages of imprecise multiplier which is essential for reducing the critical path delay, complexity and power consumption, higher compressor adders are employed. In this paper, a novel comparison technique for approximation is implemented using a 5:3 compressor which is area, power, and delay efficient. This compressor is used for developing an 8x8 multiplier. Then the proposed 8x8 multiplier and the existing multiplies are compared for various factors including the evaluation analysis of error rate (ER) and normalised error distance (NED). When compared to existing designs, the proposed 5:3 compressor has a better delay of 18%. After image multiplication, the recommended multiplier is utilised to compare PSNR.

Synthesis and analysis of a hybrid high step-up DC/DC converter with a single inductor

For low power lighting applications using Light-Emitting Diodes (LEDs), we propose a new hybrid single inductor boost converter in this paper. Unlike traditional drivers, the proposed LED source driver has a topology that fuses a Boost converter (BC) and a hybrid Cockcroft–Walton/ Dickson converter (HCWDC). The fusion of BC and HCWDC allows for high gain and few components as well as easy control. The properties of the proposed converter, which consists of 2 modules with 2 multiplier stages, are clarified by theoretical analysis and circuit simulations. Moreover, we implement the prototype on a breadboard. In the evaluations, the proposed driver achieves higher efficiency and fewer components than the existing single inductor LED drivers.

A 7.2-mW V-Band Frequency Doubler With 14% Total Efficiency in 130-nm SiGe BiCMOS

Low-voltage and low-power frequency multiplier blocks used in millimeter-wave RF frontends suffer from high conversion loss leading to lower overall efficiency. In this letter, an alternative approach in the design of a low-power <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> -band frequency doubler (FD) block without requiring an additional buffer stage is presented. The transconductance stage of a conventional Gilbert multiplier is replaced by a passive trifilar transformer serving as a power splitting, matching, and biasing network. The switching quad transistors are biased with the lowest possible dc current which still provides a positive conversion gain. Experimental results show that the circuit implemented in a 130-nm SiGe BiCMOS technology achieves 14% total efficiency at 58 GHz for an input power of 0 dBm while consuming only 7.2 mW of dc power. The measured saturated output power is 2 dBm and the measured fundamental rejection ratio (FRR) is 49 dBc. To the best of the authors’ knowledge, the lowest power consumption while maintaining a positive conversion gain among high FDs based on silicon is reported.

An Optimal Structure for High Step-Up Nonisolated DC–DC Converters With Soft-Switching Capability and Zero Input Current Ripple

In this article, an optimal structure for a high step-up nonisolated dc–dc converter is proposed. In this topology, the required high voltage gain can be obtained with a low number of elements. Furthermore, by implementing an auxiliary circuit, zero-voltage switching condition for the switches is provided, input current ripple has been reduced to almost zero, and all of the power diodes turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> under zero-current conditions. In the proposed structure, to regulate voltage gain, the extendable number of diode–capacitor voltage multiplier (DCVM) stages are combined with a coupled inductor. The voltage stresses across the semiconductors can be regulated by the number of the DCVM stages and the turns ratio of the coupled inductor. Thus, it provides two degrees of freedom for the designer to use low-rated semiconductors, which increases the converter efficiency. In this article, the performance of the proposed converter, in terms of voltage stress, voltage gain, and efficiency, has been analyzed, and a comprehensive comparison between the presented topology and other similar topologies presented. Finally, to verify the performance of the proposed topology, a 500 W (40 V/400 V) laboratory prototype has been developed and tested. The experimental results confirm its superiority and suitability.

Development and research of a multistage hydraulic gear-multiplier drive for metallurgical presses

The paper presents one of the solutions to reduce the installed power and increase efficiency of hydraulic pump drive of high power pressing equipment used in metallurgical plants. The authors have developed a multistage hydraulic drive based on a block gear-multiplier. Plungers of all cylinders form a movable block, the cylinders – a stationary one. The mode of operation (reduction, multiplication) is provided by a combination of output cylinders supplying fluid to the power cylinder by switching some of them to drain. Analysis of a four-stage drive with a three-stage multiplier gearbox is presented in comparison with a simple pump drive. A four-stage drive with two output cylinders provides a reduction gear and two multiplier stages, with which a stage of fluid supply to the power cylinder directly from the pumps (pump stage) is combined. Power and kinematic parameters of the drive were determined by the power loading during the working stroke and speed mode during the working cycle (forward (idle and working stroke) and reverse stroke). It is advisable to use a multi-stage drive with a smoothly increasing load over the entire length of the working stroke (upsetting, drawing operations). Analysis of the basic and additional combination of stages for linearly increasing power load, which was determined by the pressure at the beginning of Р0 , and the maximum pressure at the end of the working stroke Рmax was carried out. In the basic version, a gear stage (idle stroke), pump stage and two multiplier stages (working stroke) are sequentially combined. With an additional combination, the reduction stage covers idle stroke and initial part of the working stroke. Analysis was carried out under the condition of equality of pressure and power of the pumps in stages and the condition of equality of direct stroke time of the compared drives. The ratio of pump capacities was estimated. Dependences of the main parameters of the developed drive, reduction and multiplication factors were obtained. With the accepted initial data, it is possible to reduce the pressure and power of the developed drive pumps (in comparison with the simple one) by 28 – 37 % with an additional combination of stages (increases with an increase of an idle stroke). It is lower for the basic combination by 5 – 9 % (reduction is greater at lower idle stroke values). The use of an additional combination is limited by the ratio P0/Pmax ≤ 0/4.

Thermoelectric energy harvesting using a single inductor DC/DC converter employing a negative Dickson multiplier

Thermoelectric energy harvesting is the concept to convert thermal energies in an electric power. For the thermoelectric energy harvesting, a single inductor dc/dc converter using a negative Dickson multiplier is presented in this research. By merging a negative Dickson multiplier into a buck-boost converter, high voltage gain, flexible output tuning, and small power loss are attained by the proposed topology. Moreover, fewer number of switch drivers and simpler switching control are achieved than conventional hybrid boost converters, because the proposed converter with a single inductor has only one transistor switch. Through theoretical analysis, a characteristic investigation is performed regarding an example of the proposed converter with 6 diodes, 6 capacitors, a MOS-switch and an inductor, where simple formulas to clarify the converter characteristics are derived by utilizing a four-port model. Furthermore, we justify the efficacy of the proposed topology by performing the comparison among hybrid dc/dc converters with a single inductor, namely, the hybrid converter using a voltage doubler and the hybrid converter using a Cockcroft–Walton multiplier. In the comparison, computer simulations using a SPICE simulator reveal that the proposed converter achieve the best performance the compared converters. Specifically, the efficiency of the proposed converter with three multiplier stages reaches about 84% when the voltage gain is 6 and the output power is 2 W. Furthermore, some experiments verify the possibility of realization by assembling the proposed converter with three multiplier stages on a printed circuit board (PCB). In laboratory tests, maximum power efficiency of 85% and the maximum voltage gain of 6.4 are measured.

Closed-Loop Control of a New High Step-Up Multi-Input Multi-Output DC-DC Converter

Abstract: A new multi-input multi-output dc-dc converter with high step-up capability for wide power ranges is proposed in this paper. The converter's number of inputs and outputs is arbitrary and independent of each other. The proposed topology combines the benefits of DC-DC boost and switched-capacitor converters. The number of input, output, and voltage multiplier stages is arbitrary and depends on the design conditions. First, the various operating modes of the proposed converter are discussed. The closed-loop control system also must be designed using state space representation and small-signal modelling. Finally, the operation of the proposed converter is derived from the simulation results. Keywords: High power converter, Low voltage stress, Multi-Input Multi-Output (MIMO) converter, Non-isolated high step-up dc-dc converter, closed loop control.

A High Voltage Multiplier Using Stacked Hybrid Cockcroft– Walton/Dickson Multipliers

A high voltage multiplier is one of the most important components for shockwave non-thermal food processing systems. In the design of the high voltage multiplier for shockwave non-thermal food processing systems, not only high voltage gain but also high speed operation and low voltage stress of circuit components are required. In this paper, a novel high voltage multiplier with stacked topology is proposed for shockwave non-thermal food processing systems. Unlike conventional high voltage multipliers, the proposed multiplier is designed by stacking hybrid Cockcroft-Walton/Dickson multipliers (HCWDMs). In the proposed multiplier, high speed operation is achieved, because the stacked topology can reduce the number of multiplier stages. Furthermore, voltage drop of higher multiplier stages and voltage stress are mitigated by the stacked topology using HCWDMs. The validity of the circuit design is confirmed by the laboratory experiments regarding the prototype of the shockwave non-thermal food processing system. The experimental results demonstrate that the proposed multiplier can generate about 3.9 kV within 113 s by converting the ac input 100 V at 60 Hz.

Lower-Extremity Segment-Length Prediction Accuracy of the Sanders Multiplier, Paley Multiplier, and White-Menelaus Formula.

Several methods are available to estimate leg lengths at maturity to facilitate the determination of timing of epiphysiodesis. We compared the Paley multiplier, Sanders multiplier, and White-Menelaus methods in an epiphysiodesis-aged cohort. We assessed intra- and interrater reliability for Sanders skeletal stages and Greulich and Pyle atlas skeletal age. Actual growth was recorded in healthy, unoperated femoral and tibial segments from an epiphysiodesis database. The predicted and actual lengths were compared with use of the Paley multiplier and White-Menelaus methods, Greulich and Pyle skeletal age, and the Sanders multiplier using Sanders stages. Intra- and interrater reliability were assessed in a separate group of 76 skeletal age films. The cohort included 148 femora and 195 tibiae in 197 patients. Femoral length at maturity was slightly underestimated by the Sanders multiplier and staging, was overestimated by the Paley multiplier and skeletal age, and was most accurately predicted with use of the White-Menelaus formula and skeletal age. All methods overestimated tibial length at maturity. The whole-leg prediction accuracy of the Sanders multiplier and White-Menelaus formula were comparable and were more accurate than that of the Paley multiplier. For Sanders skeletal staging, the interrater reliability varied from 0.86 to 0.88 and the intrarater reliability varied from 0.87 to 0.96. For Greulich and Pyle skeletal age, the interrater reliability varied from 0.87 to 0.89 and the intrarater reliability varied from 0.91 to 0.95. Use of the Sanders multiplier and skeletal stages was more accurate than the Paley multiplier and skeletal age in this cohort. Use of the White-Menelaus formula and skeletal age was slightly more accurate in predicting femoral length and slightly less accurate in predicting tibial length compared with the Sanders multiplier. Intra- and interrater reliability were similar between Sanders skeletal stages and Greulich and Pyle atlas skeletal age. The White-Menelaus formula and skeletal age was the recommended method for predicting lower-extremity segment lengths at maturity and epiphysiodesis effect. Although easier to recall without referencing an atlas and not sex-specific, Sanders skeletal staging does not correspond directly to years of growth remaining, and thus cannot be used with the White-Menelaus formula. The Greulich and Pyle atlas to determine skeletal age and the White-Menelaus formula to determine growth remaining are reliable predictors of epiphysiodesis effect in the lower extremities.