A 7.2-mW V-Band Frequency Doubler With 14% Total Efficiency in 130-nm SiGe BiCMOS

Abstract

Low-voltage and low-power frequency multiplier blocks used in millimeter-wave RF frontends suffer from high conversion loss leading to lower overall efficiency. In this letter, an alternative approach in the design of a low-power <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> -band frequency doubler (FD) block without requiring an additional buffer stage is presented. The transconductance stage of a conventional Gilbert multiplier is replaced by a passive trifilar transformer serving as a power splitting, matching, and biasing network. The switching quad transistors are biased with the lowest possible dc current which still provides a positive conversion gain. Experimental results show that the circuit implemented in a 130-nm SiGe BiCMOS technology achieves 14% total efficiency at 58 GHz for an input power of 0 dBm while consuming only 7.2 mW of dc power. The measured saturated output power is 2 dBm and the measured fundamental rejection ratio (FRR) is 49 dBc. To the best of the authors’ knowledge, the lowest power consumption while maintaining a positive conversion gain among high FDs based on silicon is reported.