Design of High speed Multiplier using Input Scrambled 5-3 compressor for Error Tolerant image processing

Abstract

The imprecise multiplier has received a lot of attention for many high-performance systems used today such as in Image Processing, Microprocessors where multiplication is one of the fundamental operations. In order to shorten the reduction stages of imprecise multiplier which is essential for reducing the critical path delay, complexity and power consumption, higher compressor adders are employed. In this paper, a novel comparison technique for approximation is implemented using a 5:3 compressor which is area, power, and delay efficient. This compressor is used for developing an 8x8 multiplier. Then the proposed 8x8 multiplier and the existing multiplies are compared for various factors including the evaluation analysis of error rate (ER) and normalised error distance (NED). When compared to existing designs, the proposed 5:3 compressor has a better delay of 18%. After image multiplication, the recommended multiplier is utilised to compare PSNR.