Stage Operational Amplifier Research Articles

Design and Analysis of High Gain Dual Stage Op-amp in Cadence 180 nm Technology

Abstract: Operational amplifier contains basic current mirror and dual input differential amplifier. Basic Current mirror is an electronic circuit which contains two transistors. The operation of the current mirror is that whenever current is applied to drain of one of the transistors with some magnitude same current will produce at the output of another transistor, hence the name mirror of the input signal. Operational amplifier contains two legs- inverting leg, non- inverting leg. If signals are applied to inverting and non-inverting legs , operational amplifier used as an amplifier and comparator or adder or subtractor. A two stage operational amplifier consists of a differential amplifier at the input stage.While the second stage is a high gain stage biased by the output of differential amplifier.

Design, Simulation and Comparative Analysis of Two Stage Operational Amplifier Based on CNTFETs Using Indirect Feedback Frequency Compensation

In the course of this study, an efficient implementation of a high gain and low power two-stage operational amplifier using indirect feedback frequency compensation based on CNTFETs. HSPICE software was used to develop and simulate CNTFETs. The op-amps were designed using 0.9[Formula: see text]V input supply voltage. The proposed structures were formed either using CNTFETs only known as pure CNTFET-IFFC-2SOA or hybrid structures consisting a mix of both CNTFETs and conventional CMOS named as PCNTFET-NMOS-IFFC-2SOA and NCNTFET-PMOS-2SOA. The comparative investigation revealed that CNT-based structures performed significantly better than the traditional CMOS-based devices. In the instance of CNTFET-IFFC-2SOA, there was a considerable improvement in DC gain, power dissipation, phase margin, and CMRR. The DC Gain increased by 140.92%, the CMRR increased by 32.94%, and the phase margin increased by 4.9%. Furthermore, at the 32[Formula: see text]nm technology node, a GNRFET-based structure was designed and compared to conventional CMOS and pure CNTFET-based IFFC-2SOA. It was discovered that the DC gain, phase margin, and power dissipation obtained by the CNTFET-based structure were superior to both. The DC Gain of CNTFET-IFFC-2SOA was 156.79% more than that of GNRFET-IFFC-2SOA. To confirm the workability of the proposed circuits, an integrator was designed and simulated as its application. The CNTFET-based IFFC-2SOA integrators showed better integration action than the traditional CMOS-IFFC-2SOA.

Low power three-stage OTA using reverse nested frequency compensation without nulling resistor

This study introduces a novel reverse nested miller compensated high gain three stage operational transconductance amplifier (OTA) that exhibits lower power consumption and maximum allowable voltage swing. In this context, two amplifiers have been employed. The initial amplifier employs PMOS as the primary amplifying component, with a specified IDD value of 200 A. In the subsequent stages, both the second and third amplifiers are biased to operate at a current level of 2 times IDD. These operations are conducted within a 45 m Cadence Virtuoso environment. The other three-stage amplifier employs PMOS as the primary amplifier, with a bias current (IDD) of 4 μA. In a 90 m Cadence Virtuoso environment, both the second and third stages are biased to operate at a current of 5 times IDD. The primary design criteria introduced in this design approach are gain, phase margin, and power consumption, which are thoroughly stated. The circuits undergo Monte Carlo and corner evaluations, and the findings are deliberated about in the conclusion of the research. In order to attain the greatest allowable voltage swing, these amplifiers are fabricated with VDD values of 500 m and 900 m. The output voltage is set to a constant value of VDD/2.

Synthesis of signal formation and processing blocks of diffuse light reflection sensor using FPGA PSoC5 microcontroller

The problem of partial implementing the functionality of the electronic blocks for forming and processing the diffuse light reflection sensor's signal using an FPGA-microcontroller PSoC5 is solved. The topicality of this problem is caused by necessity of precision and high resolution measurement of the difference between, on the one hand, the reference signal of light reflection from the clear sensor's working surface and, on the other hand, the signal of diffuse light reflection from the inspected corroded surface. For this purpose, in particular, a channels' multiplexer, measuring and reference operational amplifiers of the second stage, a delta-sigma ADC with differential inputs, as well as a PWM control and synchronization scheme are implemented on the built into microcontroller FPGA consisting of universal digital blocks (UDB) together with programmed logical devices (PLD). The only components implemented outside the FPGA-microcontroller are the first stage operational amplifiers (in amount of sixteen), the current pulses generator for LED, as well as power supply block. The combination of components synthesized on FPGA with a powerful 32-bit Arm Cortex-M3 core makes it possible to ensure flexibility of settings, to minimize the influence of dark currents of sensitive elements of the sensor's photodiode linear array as well as noises, to align programmatically the sensitivity of the measuring channels and to carry out sensor calibration. Thus, noise mitigation is implemented programmatically by ADC's data collection and averaging in measurement buffer or calibration buffer (for reference signal from clear working surface). Several software routines for mode selection and settings, channels scanning (including measurement and calibration with alignment), as well as for measurement data (difference between the measurement and calibration buffers) displaying and transfer to PC (via one of onboard communication devices) have been developed. These all features can allow implementing the algorithms for deep analysis of measurement data and for calculation of the characteristics of surface corrosion defects.

Design and simulation of high gain two stage operational amplifier using 180n technology with Nano range

In this study, two different types of op-amps were designed and tested at a lower voltage. These op-amps use less power and can be used at a lower voltage than traditional op-amps, which makes them a good option for certain applications. The designer predicted that the power output would be high when there is a high voltage supply, and LT Spice software was used to analyze the design. Today, low-powered operational amplifiers are in high demand for many applications, such as in medical and communication systems. Some of the reasons why op-amps are in high demand are because they are versatile and have a wide range of applications. Additionally, they are often less expensive than more powerful amplifiers, which makes them a good option for certain applications. This op-amp has a good phase margin, so it can handle large loads with ease. It was created using a 180-millisecond process and CMOS technology. A 3-pF compensation capacitor and a 10-pF load capacitor are suitable for it, as the op-amp has a phase margin of 90.84 degrees...

Analysis and Comparison of Two Stage and Single Stage Operational Amplifiers Using 0.18µm Technology

Operational amplifier exists in many numbers of configurations. The there are many types of the Operational amplifiers. These are: two stage, single stage, three stage and multistage amplifiers. Identifying the better op amp is important to get better application. The better op amp will be selected by considering the performance parameters (DC Gain, Slew Rate, Power Dissipation, etc.) of op amp. In project work a two stage cmos and single stage CMOS operational has been compared and contrasted based on values of their performance parameters by using 0.18µm CMOS technology and the same power supply (5V). Based on these values, By comparing the performance parameters single stage CMOS op amp is more stable and operate longer duration of time than two stage cmos op amp with small energy loss; while two stage op amp produces the output which is twice larger than single stage op amp, and also the noise in the output of two stage op amp is less than single stage op amp. So to get more output it is better to use two stage op amps. By results and reasons suitable choices for high gain and high performance applications are two stage topologies.

Systematic design of CNTFET based OTA and Op amp using gm/ID technique

This paper presents for the first time all the steps required in optimal design of carbon nano tube field effect transistor (CNTFET) based single stage operational transconductance amplifier and two stage operational amplifier using transconductance to drain current ratio ($$g_{m}/I_{D}$$) technique for low voltage and low power applications. As square law model failed to produce exact behavior in short channel devices as well as moderate and weak inversion behavior of the transistor. Therefore, $$g_{m} / I_{D}$$ methodology is used to design analog circuits in short channel devices to overcome the shortcomings of square law models. Also, the design using $$g_{m} / I_{D}$$ methodology does not consider the inversion region of the transistor like square law equations. The $$g_{m} / I_{D}$$ methodology is a well-established technique for CMOS analog IC design but CMOS has continuous width while CNTFET width is discrete and depends on different parameters like number of tubes, pitch and diameter of the carbon nanotube. Therefore, there is a need of a design methodology to design analog circuits using CNTFETs. Circuit performance has been investigated extensively using HSPICE simulation.

Design of a Two Stage Operational Amplifier with Zero Compensation for Accurate Bandgap Reference Circuit

Design of a Two Stage Operational Amplifier with Zero Compensation for Accurate Bandgap Reference Circuit

Design an operational amplifier as a building block of analog to digital converter in 350 nm technology

In this research paper design & simulation of 2 - stage operational amplifier operates at 3.1V to 4.2V power supply at 350nm CMOS technology. This design of two stage op amp gives the application of high gain, 3dB frequency, settling time, ICMR range, CMRR range, Unity gain frequency, phase margin. Design and simulations results are verified using Mentor Graphic Tool. Discrete prototypes of operational amplifiers are used to verify the theory. This circuit is used to help for implement the “ANALOG TO DIGITAL CONVERTER”. It is the very important block of ADC.

Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level

In this paper, a low band gap material and hetero-dielectric based silicon germanium source nano wire TFET (SiGe-S-NW-TFET) is created and compared with conventional silicon nano wire TFET (Si-NW-TFET). Both devices are analysed for its DC and RF/Analog performance. Proposed device achieves higher ON-current and steeper characteristic. Simulated results of RF analysis validate the device suitability for analog application as it attains high transconductance, cut-off frequency and GBP. Apart from this, linearity analysis is also done in terms of various FOMs like higher order of gm, second-order voltage intercept point, third-order voltage intercept point and third-order intermodulation distortion. Furthermore optimization of proposed device is also done for different diameter and channel length. For checking the device suitability in low power application two stage operational amplifier is implemented using unique characteristic of SiGe-S-NW-TFET which exhibits a high gain, high PSRR and GBW of 90.5 db, −47.4 dB and 78.61 MHz respectively. The objective of this paper is to attract the attention of semiconductor industry to find opportunity beyond CMOS technology. As NW-TFET structure has very low OFF-current it consumes very low power of 4.45 μW which ensures device applicability in low power application.

Design and Analysis of Low Power VCO Enabled Quantizer for CT Sigma Delta ADC

This paper presents design and analysis of low power Voltage Controlled Oscillator (VCO) enabled quantizer in Continuous Time (CT) Sigma Delta Analog to Digital converter (ADC) using 180nm CMOS technology using Cadence Virtuoso Tool. The VCO based quantizer in Σ-Δ ADC includes loop filter, VCO quantizer and 3-bit feedback Digital to Analog Converter (DAC). The basic building block of loop filter is Operational Amplifier (OP-AMP). The two stage OP-AMP designed offers 61.51 dB gain with the unity gain bandwidth of 30.59MHz. The keystone of the ADC is VCO based qauntizer clocked at 27.34MHz, which obtains fourth order noise shaping of its quantization noise. A low power VCO is designed using seven stage ring oscillator and Logic Structure Reduction Flip Flop (LRFF) based D-Flip Flop. The VCO based qauntizer with CT Σ-Δ ADC consumes a power of 2.57 m W with a supply voltage of 1.8V.

Analysis of subthreshold SOI FinFET based two stage OTA for low power

In this paper, subthreshold design and analysis of Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) based two stage Operational Transconductance Amplifier (OTA) is presented for low power and low supply voltage in nanometre regime. The OTA design optimization is achieved by $$g_{m}/I_{D}$$ methodology which helps to determine the device aspect ratios. Compactness is achieved by using nanometre FinFET technology. The OTA design is simulated using 30 nm SOI FinFET Berkeley Short-channel IGFET Common Multi-gate (BSIM-CMG) model, with bias current and supply voltage of 20 nA and $$\pm 0.5 V$$ ;respectively. The simulation results in subthreshold regime of FinFET based two stage OTA has a gain of 57 dB with a phase margin of 69.81 degree, Common Mode Rejection Ratio (CMRR) of 61.55 dB and power consumption of 108 nW.

Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

This study presents a new placement and routing method for analogue integrated circuit layout generation based on an evolutionary algorithm, which is called modified cuckoo optimisation algorithm. Layout parasitic effects are taken into account to ensure that the performance of the circuit is not deteriorated. In order to verify the performance of the proposed method, layouts of three different circuits including differential to single-ended amplification stage, two-stage and three-stage operational amplifiers (op-amps) are automatically generated in a 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show the efficiency of the proposed algorithm in the analog layout generation.

A Novel Class AB CMOS Operational Amplifier

A novel class AB two stage operational amplifier was presented to deal with the problem of the conventional class A two stage operational amplifier’s limited slew rate. The output stage quiescent current was controlled accurately and the slew rate and unity gain bandwidth were enhanced significantly, along with no additional static power dissipation. Simulation results show that the positive and negative slew rates were raised to 35 and 2.2 times and unity gain bandwidth was raised to 5 times when compared with conventional class A operational amplifier.

Analog circuit optimization using adjoint network based sensitivity analysis

Performance optimization as per the desired specifications is a major requirement of analog and mixed signal circuit design process. Rapid scaling of the semiconductor technology demands efficient optimization techniques with minimal manual efforts. In this paper, a gradient based method for analog circuit optimization using adjoint network based sensitivity analysis is presented. The sensitivity of circuit response with respect to the different parameters is computed by using analog circuit and its adjoint transformation. The proposed method is applied to optimize performance of a two stage operational amplifier (OpAmp). Subsequently, the OpAmp circuit is simulated using Cadence Virtuoso for optimized parameters and the results are validated with post fabrication measurement results.

A Study of Two Stage Operational Transconductance Amplifier using Floating gate MOSFET

A Study of Two Stage Operational Transconductance Amplifier using Floating gate MOSFET

Two Stage Operational Amplifier with a Gain Boosted, Source Follower Buffer

Two Stage Operational Amplifier with a Gain Boosted, Source Follower Buffer

Power and Area Efficient Pipelined ADC Stage in Digital CMOS Technology

ABSTRACTA power and area efficient metal-oxide semiconductor field-effect transistor (MOSFET)-only 1.5-bit fully differential pipelined analog-to-digital converter (ADC) stage is proposed and designed in TSMC 0.18 μm digital CMOS technology with supply voltage of 1.8 V. It is based on charge pump based technique to achieve the stage voltage gain of 2. Various capacitances are implemented by MOSCAPs (capacitance offered by the MOSFET), offering compatibility with cheaper digital complimentary metal-oxide semiconductor (CMOS) process in order to reduce the much required manufacturing cost. The proposed stage suffers from only linear gain error with full signal swing of 2 V peak-to-peak (p–p) differential. Using the proposed stage, un-calibrated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) for 10-bit, 100 MS/s pipelined ADC are 40.11 and 40.86 dB, respectively, which can be further increased by using a simple digital calibration technique. Comparison between the proposed stage and conventional operational amplifier based stage shows insensitivity towards capacitor mismatch along with power savings and design simplicity.

Design and Simulation of High Performance Carbon Nanotube Based Three Stage Operational Amplifiers

In this paper, we design novel three stage operational amplifiers (3SOA). The proposed 3SOAs uses 45 nm technology node carbon nanotube field effect transistors (CNTFET) as well as the conventional MOSFETs. The proposed structures are hybrid in nature, as they use conventional MOSFETS as well as CNTFETs. The simulation study has shown that a significant improvement in DC gain, output resistance and power consumption in the proposed hybrid devices in comparison to the conventional devices. It has been observed that by varying the number of CNTs, the performance of the proposed 3SOAs can be optimized further.

Molecular Electronic Angular Motion Transducer Broad Band Self-Noise

Modern molecular electronic transfer (MET) angular motion sensors combine high technical characteristics with low cost. Self-noise is one of the key characteristics which determine applications for MET sensors. However, until the present there has not been a model describing the sensor noise in the complete operating frequency range. The present work reports the results of an experimental study of the self-noise level of such sensors in the frequency range of 0.01–200 Hz. Based on the experimental data, a theoretical model is developed. According to the model, self-noise is conditioned by thermal hydrodynamic fluctuations of the operating fluid flow in the frequency range of 0.01–2 Hz. At the frequency range of 2–100 Hz, the noise power spectral density has a specific inversely proportional dependence of the power spectral density on the frequency that could be attributed to convective processes. In the high frequency range of 100–200 Hz, the noise is conditioned by the voltage noise of the electronics module input stage operational amplifiers and is heavily reliant to the sensor electrical impedance. The presented results allow a deeper understanding of the molecular electronic sensor noise nature to suggest the ways to reduce it.