Low power three-stage OTA using reverse nested frequency compensation without nulling resistor

Abstract

This study introduces a novel reverse nested miller compensated high gain three stage operational transconductance amplifier (OTA) that exhibits lower power consumption and maximum allowable voltage swing. In this context, two amplifiers have been employed. The initial amplifier employs PMOS as the primary amplifying component, with a specified IDD value of 200 A. In the subsequent stages, both the second and third amplifiers are biased to operate at a current level of 2 times IDD. These operations are conducted within a 45 m Cadence Virtuoso environment. The other three-stage amplifier employs PMOS as the primary amplifier, with a bias current (IDD) of 4 μA. In a 90 m Cadence Virtuoso environment, both the second and third stages are biased to operate at a current of 5 times IDD. The primary design criteria introduced in this design approach are gain, phase margin, and power consumption, which are thoroughly stated. The circuits undergo Monte Carlo and corner evaluations, and the findings are deliberated about in the conclusion of the research. In order to attain the greatest allowable voltage swing, these amplifiers are fabricated with VDD values of 500 m and 900 m. The output voltage is set to a constant value of VDD/2.