Gate Stack Research Articles

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Improved lateral figure-of-merit of heteroepitaxial α-Ga2O3 power MOSFET using ferroelectric AlScN gate stack

In this Letter, we demonstrate heteroepitaxial α-Ga2O3 MOSFETs using an aluminum scandium nitride (AlScN) ferroelectric gate stack. Owing to ferroelectric effects, α-Ga2O3 MOSFETs with the AlScN/HfO2 gate stack (FGFET) exhibited enhanced electrical performance compared with a HfO2 gate dielectric (IGFET) for variable gate–drain lengths (10, 15, 20 μm). A remnant polarization value of the AlScN deposited on a HfO2 layer was measured to be about 30 μC/cm2. The subthreshold swing (SS) and field-effect mobility (μFE) of IGFET was extracted at 1814 mV/dec and 13.9 cm2/V s, respectively. However, the FGFET exhibits a reduced SS of 552 mV/dec with enhanced μFE of 42.7 cm2/V s owing to the negative capacitance of the ferroelectric AlScN. Furthermore, a lateral figure-of-merit of 17.8 MW/cm2 was achieved for the FGFET, far surpassing the 8.3 MW/cm2 of the IGFET. The proposed ferroelectric AlScN/HfO2 stack can be a promising gate structure for improving both transfer and breakdown characteristics in heteroepitaxial α-Ga2O3 power devices.

Impact of monolayer WS2 surface properties on the gate dielectrics formation by atomic layer deposition

Two-dimensional transition metal dichalcogenides (2D TMDs), such as MoS2 and WS2, have emerged as promising channel materials for future generation transistors. However, carbon-based surface contaminants pose a significant challenge in the formation of high-quality metal–oxide–semiconductor gate stacks for 2D TMDs. Carbon-based surface contaminants are known to be present even on directly grown 2D TMDs that have not been in contact with polymers. These organic contaminants affect precursor adsorption during atomic layer deposition (ALD) of gate dielectrics on 2D TMDs and as such the 2D-dielectric interface. This study examines the effectiveness of predeposition annealing in mitigating carbon-based contaminants while maintaining the integrity of a directly grown WS2 monolayer on a SiO2 substrate. We show that a WS2 monolayer on a SiO2/Si substrate remains stable during vacuum annealing at temperatures up to 400 °C. Water contact angle measurements and x-ray photoelectron spectroscopy confirm that the surface concentration of carbon starts to decrease at 150 °C. Thermal anneal improves the surface coverage of Al2O3 for both conventional chemisorption-based ALD and physisorbed-precursor-assisted ALD processes by facilitating more effective Al2O3 nucleation on the WS2 monolayer. The impact of predeposition anneal on the Al2O3 growth behavior in both processes can be explained by changes in surface contaminant levels. Our results underscore the importance of surface pretreatment in dielectric deposition on 2D TMDs and demonstrate that predeposition anneal is an effective method to enhance ALD-based dielectric deposition on directly grown 2D TMDs.

Simulation of silicon conical field effect GAA nanotransistors with stack SiO2/HfO2 dielectric of gate

The issues of modeling the electrophysical characteristics of a silicon conical field effect GAA nanotransistor are discussed. An analytical model of the drain current of a transistor with a fully enclosing conical gate with a stack sub-gate oxide SiO2/HfO2 has been developed, taking into account the effect of the charge of the interphase trap at the Si/SiO2 interface. To simulate the potential distribution in a conical working area under the condition of constant trap density, an analytical solution of the Poisson equation was obtained using the method of parabolic approximation in a cylindrical coordinate system with appropriate boundary conditions. The potential model was used to develop an expression for the GAA drain current of a nanotransistor with a stack gate oxide. The key electrophysical characteristics are numerically investigated depending on the density of traps and the thicknesses of SiO2 and HfO2 layers.

Dielectric Modulated Nanotube Tunnel Field-Effect Transistor with Core-Shell Cavity as a Label-Free Biosensor: Proposal and Analysis.

Dielectric Modulated Field-Effect Transistors (DMFETs) have emerged as promising candidates for label-free bioanalyte detection. However, the inherent short-channel effects in conventional DMFETs increase their static power dissipation significantly and limit their scalability and sensitivity. Therefore, FETs based on alternate conduction mechanism such as tunneling (TFETs), which are immune to the short-channel effects, appear to be a lucrative alternative to the MOSFETs for biosensing application. In this work, we propose a novel Dual Cavity Dielectric Modulated Nanotube Tunnel FET (DCDM NTTFET)-based label-free biosensor consisting of a Ge source and nanocavities within the core as well as a shell gate stack, which not only outperforms the conventional MOSFET and advanced nanowire (NW) TFET-based biosensors in terms of energy-efficiency and scalability but also exhibits a significantly high drain current sensitivity (SION = 2.9 × 108) and a threshold voltage sensitivity (SVth = 0.85), and a considerably high selectivity of more than 6 orders of magnitude. We also perform a comprehensive design space exploration for the proposed DCDM NTTFET and provide necessary design guidelines to further improve its performance considering the practical artifacts such as steric hindrance.

Low Contact Resistance WSe2 p-Type Transistors with Highly Stable, CMOS-Compatible Dopants.

High contact resistance has been a bottleneck in developing high-performance transition-metal dichalcogenide (TMD) based p-type transistors. We report degenerately doped few-layer WSe2 transistors with contact resistance as low as 0.23 ± 0.07 kΩ·μm per contact by using platinum(IV) chloride (PtCl4) as the p-type dopant, which is composed of ions compatible with the complementary metal-oxide-semiconductor (CMOS) fabrication process. Top-gated devices with a gate length of 200 nm showed good switching behaviors, implying that the dopant diffusion into the gate stack is not significant. The devices showed nearly identical performance after being kept in air for 86 days without any encapsulation while retaining the degenerately doped states at 78 K with pressure lower than 10-5 Torr, highlighting the stability of the dopants. The presented method sets forth the availability of highly stable methods for pattern doping the transistors with a thinned Schottky barrier width for low contact resistance devices.

A Study on the Channel Holes’ Diameter Effects of High-Performance Vertical-Channel Flash Memory Cells

Abstract High-performance vertical-channel flash (HVF) memory cells were fabricated on the single crystalline Si (c-Si) sidewalls of the cylindrical deep wells in c-Si substrate. To investigate the diameter effects of the cylindrical deep wells, namely channel holes, on HVF cells, the channel holes with different diameters, ranging from 65 nm to 260 nm, were made. Memory gate stacks of SiO2/ Al2O3/HfO2/Al2O3/TiN/W were formed by ozone oxidation and then ALD with the deposition thicknesses of 1/5/7/8/2/150 nm, respectively. For the devices with their diameters equal to or greater than 150 nm, their electrical properties, such as Vt, SS, DIBL, and program/erase characteristics, are close. As expected, DIBL and SS become better as the diameter increasing due to better gate control with larger diameter. However, large changes were occurred for the devices with the diameters of 90 nm and 65 nm. A simple model based on cylinder bulk for vertical flash memory devices was presented to obtain an approximate analytical solution for depletion-width and explain our experimental data. For the devices with the diameters of 150 nm, the high On/Off current ratio of 107 and relatively large memory window of 4.5 V were achieved. However, programming/erasing efficiency were degraded with hole diameter decreasing.

Physical understanding of a normally off p-GaN/AlGaN/GaN HEMT gate stack and a review of VTH measurement techniques

Abstract In this report a comprehensive review of the variations in threshold voltage (VTH) resulting from diverse VTH measurement bias conditions employed by leading manufacturers, as well as VTH extraction techniques is made. Notably, a standard deviation of 15% is observed in threshold voltage values due to variations in measurement bias conditions. This variation is attributed to the change in the lateral electic field conditions across gate and drain which occurs due to the change in bias conditions. Additionally, a simplified physical interpretation of the gate stack in p-GaN gate normally-off AlGaN/GaN on Si HEMTs is made. The formation of the two-dimensional electron gas (2DEG), the charge balance within the pGaN/AlGaN/GaN gate stack, and an analytical expression for threshold voltage are examined. Furthermore, various trapping mechanisms within the gate stack are reviewed to comprehend the dynamic conditions potentially contributing to threshold voltage instability during nominal operation.

Optimization and analysis of Si/SiGe strained vertically stacked heterostructure on insulator FeFinFET for high performance analog and RF applications

As semiconductor technology advances, the exploration of novel materials and device architectures becomes imperative to meet the growing demands of integrated circuits for analog and radio-frequency (RF) applications. In this paper, various advanced technologies have been amalgamated such as integration of ferroelectric layer in multigate FinFET along with the adaptation of SOI technology. Further strain technology is also used which employs a tri-layered strained-silicon channel system with the help of SiGe to form Vertically Stacked Heterostructure on Insulator Ferroelectric based FinFET (VS-HOI-FeFinFET) and on comparison with baseline FeFinFET, it is found to show remarkable improvements in terms of various measured parameters such as drain current, switching ratio, threshold voltage and subthreshold swing. Subsequently, gate stacking architecture is incorporated in VS-HOI-FeFinFET to further optimize the device performance. The four different configurations C1 to C4 are taken in terms of four different combinations of gate stack materials considered for gate oxide such as C1(SiO2+Al2O3), C2(SiO2+HfO2), C3(Al2O3), and C4(Al2O3+HfO2). It is found that the static and analog performance of VS-HOI-GS-FeFinFET enhance sequentially from configuration C1 to C4 such as switching ratio is enhanced upto around 5 times, DIBL and quality factor are improved by around 41% and 58% respectively along with significant improvement in device efficiency, early voltage, intrinsic gain, output conductance and output resistance. Subsequently performance optimization of VS-HOI-GS-FeFinFET with variation in mole fraction of germanium is also explored for various analog metrics. Further, several RF parameters are also explored and it is observed that the gain frequency product (GFP) and gain transconductance frequency product (GTFP) are augmented by around three times in magnitude along with 16% reduction in the unity gain cut off frequency in C4 configuration, exhibiting its ability of high frequency amplification with minimized noise distortion thus makes the device suitable for various high performance Analog and RF applications.

Multifunctional Reconfigurable Operations in an Ultra-Scaled Ferroelectric Negative Transconductance Transistor.

The integration of functional materials into electronic devices has become a key approach to extending Moore's law by increasing the functional density of electronic circuits. Here, we present a device technology based on ultrascaled ferroelectric, antiambipolar transistors (ferro-AAT) with robust negative transconductance, enabling a wide range of reconfigurable functionalities with applications in both the digital and analog domains. The device relies on the integration of a hafnia-based ferroelectric gate stack on a vertical nanowire tunnel field-effect transistor. Through intentional gate/source overlap and tunnel-junction engineering, we demonstrate enhanced antiambipolarity with a high negative transconductance that is reconfigurable using the nonvolatile remanent polarization of the ferroelectric. Experimental validation highlights the versatility of this ferro-AAT in two implementation scenarios: content addressable memory (CAM) for high-density data search and reconfigurable signal processing in analog circuits. As a single-transistor cell for CAMs, the ferro-AAT shows subpicojoule operation for one search with a compact footprint of ∼0.01 μm2. For single-transistor-based signal modulation, multistate reconfigurations and high power conversion (>95%) are achieved in the ferro-AAT, resulting in a significant reduction in the complexity of analog circuit design. Our results reveal that the distinctive device properties allow ferro-AATs to operate beyond conventional transistors with multiple reconfigurable functionalities, ultrascaled footprint, and low power consumption.

Scalable on-chip multiplexing of silicon single and double quantum dots

Owing to the maturity of complementary metal oxide semiconductor (CMOS) microelectronics, qubits realized with spins in silicon quantum dots (QDs) are considered among the most promising technologies for building scalable quantum computers. For this goal, ultra-low-power on-chip cryogenic CMOS (cryo-CMOS) electronics for control, read-out, and interfacing of the qubits is an important milestone. We report on-chip interfacing of tunable electron and hole QDs by a 64-channel cryo-CMOS multiplexer with less-than-detectable static power dissipation. We analyze charge noise and measure state-of-the-art addition energies and gate lever arm parameters in the QDs. We correlate low noise in QDs and sharp turn-on characteristics in cryogenic transistors, both fabricated with the same gate stack. Finally, we demonstrate that our hybrid quantum-CMOS technology provides a route to scalable interfacing of a large number of QD devices, enabling, for example, variability analysis and QD qubit geometry optimization, which are prerequisites for building large-scale silicon-based quantum computers.

Impact of source/drain lateral straggle on GIDL current of low SS NC-FinFET

ABSTRACT In this paper, the gate-induced drain leakage (GIDL) issue in negative capacitance (NC-FinFET) has been comprehensively addressed using Sentaurus 3-D TCAD simulations. Incorporation of ferroelectric (FE) materials in the gate stack of NC-FinFET increases with current by 12% compared to that of baseline FinFET. A steeper sub-threshold swing (SS) of 8 mV/dec is achieved at a FE-thickness of 5 nm at a lateral straggle; (σ) = 0 nm. GIDL behaviour with respect to the variation of source/drain σ and gate oxide thicknesses of NC-FinFET with and without the presence of the GateTunneling model is thoroughly investigated. Investigations demonstrate that in NC-FinFET, there are steeper energy band profiles near source/drain owing to coupling of fringing fields to the ferroelectric layer, which exhibits a larger and prior commencement of the longitudinal band to band tunnelling current compared to conventional FinFET. Moreover, the effect of variation of σ on various parameters viz. SS, capacitance and transconductance has also been investigated, which shows better results for lower σ values. At σ = 0 nm, drain-induced barrier lowering is −187.23 mV/V as compared to that of σ = 5 nm, which is −355.3 mV/V. Furthermore, we have also investigated drain current noise spectral density (SID) and gate voltage noise spectral density (SVG) with respect to fin width (WFIN) at the optimised σ value.

Hf0.4Zr0.6O2 Thickness-Dependent Transfer Characteristics of InxZn1-xOy Channel Ferroelectric FETs.

We investigate how the threshold voltage (VT) is adjusted to create a memory window (MW) in ferroelectric field-effect transistors (FeFETs) composed of ferroelectric Hf0.4Zr0.6O2 and InZnO (In2O3:ZnO = 9:1 wt %). Temperature-dependent polarization measurements reveal a dipole switching in Hf0.4Zr0.6O2. The properties of the n-type InZnO channel are examined by fabricating an oxide transistor with an HfO2 gate dielectric. Upon replacement of HfO2 with Hf0.4Zr0.6O2 in the oxide transistor, a counterclockwise MW is observed. Specifically, as the Hf0.4Zr0.6O2 thickness increases from 16 to 24 nm, the VT of the FeFET after a + gate voltage (VG) sweep remains nearly constant, while the VT after a -VG sweep shifts significantly from -0.9 to 0.5 V. The enlarged MW of approximately 2 V, which is proportional to the Hf0.4Zr0.6O2 thickness in the FeFET, can be explained by considering the balance between VG controllability across the gate stack and the ferroelectric switching of Hf0.4Zr0.6O2.

Numerical simulation of core shell dual metal gate stack junctionless accumulation mode nanowire FET (CS-DM-GS-JAMNWFET) for low power digital applications

In this paper, Core Shell Dual Metal Gate Stack Junctionless Accumulation Mode Nanowire FET (CS-DM-GS-JAMNWFET) is proposed, which has enhanced performance and is suitable for analog and digital applications. A high-k gate stack engineering, Hafnium Oxide (HfO2) is deployed in the outer as well as inner gate oxides of the core shell structure. The proposed device is compared with CS-DM-JAMNWFET, CS-SM-JAMNWFET, DM-GS-JAMNWFET, DM-JAMNWFET, and SM-JAMNWFET by maintaining a constant threshold voltage for all structures. The proposed CS-DM-GS-JAMNWFET provides a substantial reduction in subthreshold current with a high Ion/Ioff ratio as compared to other competent device structures. Also, the proposed device exhibits improvements in various parameters compared to the SM-JAMNWFET. It shows improvement in drain current (2.27 times), output conductance (2.14 times), subthreshold swing (0.94 times), transconductance (2.47 times), gate capacitance (2.00 times), cut-off frequency (1.24 times), intrinsic gain (12.95 times), current gain (1.46), Ion/Ioff ratio (6.15 times), unilateral power gain (1.09 times), maximum transducer power gain (1.08 times), Transconductance Generation factor (1.08 times), gain frequency product (14.61 times), transconductance frequency product (1.32 times), and gain transconductance frequency product (17.27 times). These benefits are due to combined advantages of the dual metal high-k dielectric HfO2 structure in core shell JAM FET, which enhances the device's gate dominance over the channel with high driving current.

Ultra-High-k Ferroelectric BaTiO3 Perovskite in the Gate Stack for Two-Dimensional WSe2 p-Type High-Performance Transistors.

The experimental demonstration of a p-type 2D WSe2 transistor with a ferroelectric perovskite BaTiO3 gate oxide is presented. The 30 nm thick BaTiO3 gate stack shows a robust ferroelectric hysteresis with a remanent polarization of 20 μC/cm2 and further enables a capacitance equivalent thickness of 0.5 nm in the hybrid WSe2/BaTiO3 stack due to its high dielectric constant of 323. We demonstrate one of the best ON currents for perovskite gate 2D transistors in the literature. This is enabled by high-quality epitaxial growth of BaTiO3 and a single 2D layer transfer based fabrication method that is shown to be amenable to silicon platforms. This demonstration is an important milestone toward the integration of crystalline complex oxides with 2D channel materials for scaled CMOS and low-voltage ferroelectric logic applications.

High-temperature operation of Al2O3/Ga2O3 bi-layer gate stack GaN MOS-HEMT up to 450 °C with suppressed gate leakage

Abstract In this work, we report the reduced gate leakage current by using aluminum oxide (Al2O3) and gallium oxide (Ga2O3) as a bi-layer gate stack for GaN MOS-HEMT on a silicon substrate up to 450 °C. The bi-layer gate stack MOS-HEMTs suppressed the gate leakage by more than four orders of magnitude compared to only Al2O3-based GaN MOS-HEMT at 450 °C. The low gate leakage current is attributed to the reduced oxygen vacancies present in the Ga2O3 layer, which effectively impede the conduction path of the Poole-Frenkel emission at high temperatures, thereby enhancing the overall performance of GaN HEMTs.

Charge trapping gate stack enabled non-recessed normally off AlGaN/GaN HEMT with high threshold voltage stability

This paper reports a non-recessed normally off AlGaN/GaN high-electron-mobility transistor (HEMT) with a charge trapping gate dielectric stack. The charge trapping gate dielectric stack featuring a low density of fixed positive charges consists of an O3-based Al2O3 tunneling layer and an O3-based HfO2 blocking layer, both deposited via atomic layer deposition. For HEMT with a 15 nm AlGaN barrier layer, a threshold voltage of 2.57 V and an on-resistance of 8.50 Ω × mm are achieved. For positive bias temperature instability (PBTI) testing, the electric field provided by the 15 nm AlGaN layer serves as a barrier to channel carriers, significantly enhancing the PBTI test stability. The optimized gate dielectric stack enables the fabrication of the non-recessed normally off metal–insulator–semiconductor-HEMT with enhanced threshold voltage (Vth) stability.

Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash

Superlattice ferroelectric-metal field-effect transistor (SL-FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for triple-level cell (TLC) operations. The SL-FeMFET shows a novel approach for designing the gate-stack using a superlattice of ferroelectric/dielectric/ferroelectric for achieving large memory window ∼3.48 V with program/erase voltage ±7 V for 3D NAND architecture. By TCAD modeling, we demonstrate TLC operation of SL-FeMFET with improving memory window and alleviating variability caused by floating metal layer in FeMFET structure. In addition, as the vertical gate stack increases from 256-layer to 512-layer, the read-out current with worst cases in seven read operations for TLC sensing are examined using page buffer circuit for sensing operation. The simulation results suggest that SL-FeMFET based 3D NAND architecture can operate 512-layer with sufficient sense margin for TLC operation.

Dielectric Modulated TFET on SELBOX Substrate as a Label-Free Biosensor Applications: Analytical Modeling Study and Sensitivity Analysis

Abstract The manuscript proposes a ferroelectric heterojunction TFET (BG-FE-HJ-STFET) on SELBOX substrates with a back gate to create an ultra-sensitive label-free biosensor with dielectric modulation for the detection of neutral and charged biomolecules. Within the proposed device, four cavities have been carved out for the biomolecules' immobilization under the front and rear gate dielectrics. By using a ferroelectric (FE) material as a gate stack, the low gate voltage is increased to be more effective by causing a negative capacitance phenomenon. The response of the proposed biosensor to four impartial biomolecules with different dielectric constants Protein (k=8), Biotin (k=2.63), 3-Aminopropyl-triethoxysilane (APTES) (k=3.57), and Streptavidin (k=0.1) has been investigated. Deoxyribonucleic acid (DNA), a charged biomolecule, is also examined for dielectric constant of k=6 with respect to both charges (Negative and Positive)) densities. The device is simulated with the commercially available SILVACO ATLASTM TCAD tool. The performance analysis relies on several figures of merit (FOMs) such as DC/RF and sensitivity (including drain current, ION/IOFF ratio, and subthreshold swing) for both neutral and charged biomolecules. The optimized cavity structure demonstrates a notable sensitivity in drain current (2.7x108) and a significant ION/IOFF sensitivity (1.42x1011). One of the main problems with current biosensors is the difficulty and expense of production in the nanoscale realm.

Energy Efficient Electrolytic-Gated Synapse Transistors Using InGaZnO/HfO2 Gate Stacks With Vertical Channel Configurations

Energy Efficient Electrolytic-Gated Synapse Transistors Using InGaZnO/HfO₂ Gate Stacks With Vertical Channel Configurations