Stack Architecture Research Articles

Analysis of floodplain sedimentation, avulsion style and channelized fluvial sandbody distribution in an upper coastal plain reservoir: Middle Jurassic Ness Formation, Brent Field, UK North Sea

Abstract Numerical models and recent outcrop case studies of alluvial-to-coastal-plain strata suggest that autogenic avulsion can control the stacking density and architecture of channelized fluvial sandbodies. The application of these models to subsurface well data was tested by the analysis of upper coastal plain deposits of the late Bajocian Ness Formation in the Brent Field reservoir, UK North Sea. These coastal plain deposits accumulated during the progradation and retrogradation of the wave-dominated ‘Brent Delta’. Sedimentological facies analysis and palaeosol characterization in cores were used to interpret the styles of palaeochannel avulsion. These results were then compared with the dimensions and distributions of channelized fluvial sandbodies that had been quantified by spatial statistical tools (lacunarity, Besag's L function) applied to interpretative correlation panels between closely spaced wells. The results indicate that the distributions of channelized sandbodies may plausibly have been generated by avulsions and that they influence sandbody connectivity and pressure depletion patterns. Intervals of upper coastal plain strata with relatively wide sandbodies that display some clustering in their stratigraphic architecture are associated with a high proportion of avulsions by incision and annexation in core samples. Such intervals display relatively good vertical pressure communication and relatively slow, uniform pressure depletion.

An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor

Modern systems-on-chip augment their baseline CPU with coprocessors and accelerators to increase overall computational capability and power efficiency, and thus have evolved into heterogeneous multi-core systems. Several languages have been developed to enable this paradigm shift, including CUDA and OpenCL. This paper discusses a unified compilation environment to enable heterogeneous system design through the use of OpenCL and a highly configurable VLIW Chip Multiprocessor architecture known as the LE1. An LLVM compilation framework was researched and a prototype developed to enable the execution of OpenCL applications on a number of hardware configurations of the LE1 CMP. The presented OpenCL framework fully automates the compilation flow and supports work-item coalescing which better maps onto the ILP processor cores of the LE1 architecture. This paper discusses in detail both the software stack and target hardware architecture and evaluates the scalability of the proposed framework by running 12 industry-standard OpenCL benchmarks drawn from the AMD SDK and the Rodinia suites. The benchmarks are executed on 40 LE1 configurations with 10 implemented on an SoC-FPGA and the remaining on a cycle-accurate simulator. Across 12 OpenCL benchmarks results demonstrate near-linear wall-clock performance improvement of 1.8 × (using 2 dual-issue cores), up to 5.2 × (using 8 dual-issue cores) and on one case, super-linear improvement of 8.4 × (FixOffset kernel, 8 dual-issue cores). The number of OpenCL benchmarks evaluated makes this study one of the most complete in the literature.

Two- and Three-Tiered Stacked Architectures by Covalent Assembly.

Simple discotic cores functionalized with reactive arms have been assembled into two- and three-tiered covalent stacks through imine formation. The targets are obtained in good yields, but competing formation of misassembled byproducts highlights some of the challenges inherent to the thermodynamically controlled assembly of rigid, compact, three-dimensional architectures. The structures comprise a central stack of arenes surrounded by a triple helix of interconnected arms. The racemization rate is strongly dependent on the number of tiers, suggesting cooperative conformational coupling in these multi-tiered structures.

Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

In this paper, the impact of asymmetric gate stack architecture using a combination of vacuum and high-k dielectrics on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET has been investigated. A comparative evaluation of short channel effects (SCEs) for various device structures has also been carried out with figure of merit (FOM) metrics such as electric field, electron temperature, drain current (Ids), and drain induced barrier lowering (DIBL). A two-dimensional analytical model has been developed for the asymmetric architecture using Poisson’s equation in cylindrical coordinates assuming a parabolic potential profile. It is observed that the asymmetric gate stack device demonstrates effectiveness in suppressing hot carrier degradation and short channel effects along with improving the current drivability of the device as compared to the other device configurations. The analytical results have been verified with the simulated data obtained from ATLAS 3-D device simulator.

Small phase pattern 2D beam steering and a single LCOS design of 40 1 × 12 stacked wavelength selective switches.

Two-dimensional beam steering by small, square, phase patterns as small as 50 × 50 pixels on a phase-only liquid crystal on silicon (LCOS) device is experimentally verified as suitable for the application of wavelength selective switches (WSSs), in terms of the diffraction efficiency and steering accuracy. This enables a proposed highly functional and versatile stacked switch architecture, where 40 independent 1 × 12 WSSs can be realised on a single 4k LCOS device. They can be configured to support a 1 × N WSSs with N≤144, or an N × N wavelength crossconnect with N≤12.

Efficient, inkjet-printed TADF-OLEDs with an ultra-soluble NHetPHOS complex

Using printed organic light-emitting diodes (OLEDs) for lighting, smart-packaging and other mass-market applications has remained a dream since the first working OLED devices were demonstrated in the late 1980s. The realization of this long-term goal is hindered by the very low abundance of iridium and problems when using low-cost wet chemical production processes. Abundant, solution-processable Cu(I) complexes promise to lower the cost of OLEDs. A new copper iodide NHetPHOS emitter was prepared and characterized in solid state with photoluminescence spectroscopy and UV photoelectron spectroscopy under ambient conditions. The photoluminescence quantum efficiency was determined as 92 ± 5 % in a thin film with yellowish-green emission centered around 550 nm. This puts the material on par with the most efficient copper complexes known so far. The new compound showed superior solubility in non-polar solvents, which allowed for the fabrication of an inkjet-printed OLED device from a decalin-based ink formulation. The emission layer could be processed under ambient conditions and was annealed under air. In a very simple stack architecture, efficiency values up to 45 cd A−1 corresponding to 13.9 ± 1.9 % EQE were achieved. These promising results open the door to printed, large-scale OLED devices with abundant copper emitters.

Editorial: Putting the "Why" Back into Bone "Archytecture".

Editorial: Putting the "Why" Back into Bone "Archytecture".

Microstructural investigation of phases and pinning properties in MBa2Cu3O7−x (M = Y and/or Gd) coated conductors produced by scale-up facilitie

To expedite the commercialization of coated conductors, a robust stacking architecture of the wires must be developed and the performance of the critical currents improved. More importantly, the manufacturability, or large-scale delivery, and the capability of sustaining production at a high rate must be considered. The products of three companies, American Superconductor, Superpower Inc., and SuNAM Co., Ltd, were selected because these companies have announced commercial-grade production lines and delivered a significant amounts of wires to the open market that meet the standards demanded by power devices. X-ray diffraction patterns were used to verify the structural properties and the phase formation in the wires, and transmission electron microscopy with energy dispersive spectroscopy was used to investigate the microstructure and composition of the conductors. In addition, Raman scattering spectroscopy was used for the analysis of the phase formation and for the elucidation of secondary phases in the superconducting layers. The field dependence of the critical current was also studied to compare the transport characteristics under relatively low and medium magnetic field at 77 K and 60 K. Pinning forces were obtained from the field dependence of transport properties and pinning characteristics were investigated. The theoretical and experimental analyses were combined together using the Dew-Hughes formula to extract the scaling exponents and estimate the irreversibility lines of the fields. The results showed that the three conductors possess pinning mechanisms that originate from core pinning with a surface pinning geometry. It is remarkable that the wires discussed in this paper exhibit very similar pinning characteristics even though they have different characteristics in terms of chemical composition, microstructure, stacking architectures, and distribution of parasitic phases.

High Speed Electroplating of 200um High Cu Bumps for Die Stacking Architectures

Recent advanced packaging architectures pose a number of challenges for metal deposition by electroplating, including shrinking RDL and pillar interconnects, via fills, and interconnect lines over topography. However, there is a class of die stacking designs which incorporate extremely tall Cu pillars, or

A synchronous Gigabit Ethernet protocol stack for high-throughput UDP/IP applications

State of the art detector readout electronics require high-throughput data acquisition (DAQ) systems. In many applications, e. g. for medical imaging, the front-end electronics are set up as separate modules in a distributed DAQ. A standardized interface between the modules and a central data unit is essential. The requirements on such an interface are varied, but demand almost always a high throughput of data. Beyond this challenge, a Gigabit Ethernet interface is predestined for the broad requirements of Systems-on-a-Chip (SoC) up to large-scale DAQ systems. We have implemented an embedded protocol stack for a Field Programmable Gate Array (FPGA) capable of high-throughput data transmission and clock synchronization. A versatile stack architecture for the User Datagram Protocol (UDP) and Internet Control Message Protocol (ICMP) over Internet Protocol (IP) such as Address Resolution Protocol (ARP) as well as Precision Time Protocol (PTP) is presented. With a point-to-point connection to a host in a MicroTCA system we achieved the theoretical maximum data throughput limited by UDP both for 1000BASE-T and 1000BASE-KX links. Furthermore, we show that the random jitter of a synchronous clock over a 1000BASE-T link for a PTP application is below 60 ps.

3D Porous Architecture of Stacks of β-TCP Granules Compared with That of Trabecular Bone: A microCT, Vector Analysis, and Compression Study.

The 3D arrangement of porous granular biomaterials usable to fill bone defects has received little study. Granular biomaterials occupy 3D space when packed together in a manner that creates a porosity suitable for the invasion of vascular and bone cells. Granules of beta-tricalcium phosphate (β-TCP) were prepared with either 12.5 or 25 g of β-TCP powder in the same volume of slurry. When the granules were placed in a test tube, this produced 3D stacks with a high (HP) or low porosity (LP), respectively. Stacks of granules mimic the filling of a bone defect by a surgeon. The aim of this study was to compare the porosity of stacks of β-TCP granules with that of cores of trabecular bone. Biomechanical compression tests were done on the granules stacks. Bone cylinders were prepared from calf tibia plateau, constituted high-density (HD) blocks. Low-density (LD) blocks were harvested from aged cadaver tibias. Microcomputed tomography was used on the β-TCP granule stacks and the trabecular bone cores to determine porosity and specific surface. A vector-projection algorithm was used to image porosity employing a frontal plane image, which was constructed line by line from all images of a microCT stack. Stacks of HP granules had porosity (75.3 ± 0.4%) and fractal lacunarity (0.043 ± 0.007) intermediate between that of HD (respectively 69.1 ± 6.4%, p < 0.05 and 0.087 ± 0.045, p < 0.05) and LD bones (respectively 88.8 ± 1.57% and 0.037 ± 0.014), but exhibited a higher surface density (5.56 ± 0.11 mm2/mm3 vs. 2.06 ± 0.26 for LD, p < 0.05). LP granular arrangements created large pores coexisting with dense areas of material. Frontal plane analysis evidenced a more regular arrangement of β-TCP granules than bone trabecule. Stacks of HP granules represent a scaffold that resembles trabecular bone in its porous microarchitecture.

Thin-dielectric-layer engineering for 3D nanostructure integration using an innovative planarization approach

Three-dimensional (3D) nanostructures are emerging as promising building blocks for a large spectrum of applications. One critical issue in integration regards mastering the thin, flat, and chemically stable insulating layer that must be implemented on the nanostructure network in order to build striking nano-architectures. In this letter, we report an innovative method for nanoscale planarization on 3D nanostructures by using hydrogen silesquioxane as a spin-on-glass (SOG) dielectric material. To decouple the thickness of the final layer from the height of the nanostructure, we propose to embed the nanowire network in the insulator layer by exploiting the planarizing properties of the SOG approach. To achieve the desired dielectric thickness, the structure is chemically etched back with a highly diluted solution to control the etch rate precisely. The roughness of the top surface was less than 2 nm. There were no surface defects and the planarity was excellent, even in the vicinity of the nanowires. This newly developed process was used to realize a multilevel stack architecture with sub-deca-nanometer-range layer thickness.

Proving Skipping Refinement with ACL2s

We describe three case studies illustrating the use of ACL2s to prove the correctness of optimized reactive systems using skipping refinement. Reasoning about reactive systems using refinement involves defining an abstract, high-level specification system and a concrete, low-level system. Next, one shows that the behaviors of the implementation system are allowed by the specification system. Skipping refinement allows us to reason about implementation systems that can "skip" specification states due to optimizations that allow the implementation system to take several specification steps at once. Skipping refinement also allows implementation systems to, i.e., to take several steps before completing a specification step. We show how ACL2s can be used to prove skipping refinement theorems by modeling and proving the correctness of three systems: a JVM-inspired stack machine, a simple memory controller, and a scalar to vector compiler transformation.

Influence of Glass Transition Temperature of Underfill on the Stress Behavior and Reliability of Microjoints Within a Chip Stacking Architecture

In this study, the reliability performance of two capillary-type underfill materials with different glass transition temperatures (Tg) and coefficients of thermal expansion (CTE) were assessed for a chip stacking architecture. The microbumps for integrating four chips on a Si interposer were with a pitch size of 20 μm and composed of 5 μm Cu/3 μm Ni/5 μm Sn2.5Ag solder cap. A thermocompressive bonder was used to interconnect the microbumps at 280 °C for 15 s, and the microgaps between the chips and the interposer were then, respectively, sealed by the mentioned underfill materials to form a chip stacking architecture. Then, the reliability characteristics of the test vehicles were evaluated following the preconditioning and temperature cycling test (TCT). Furthermore, a numerical analysis model was established by ansys software to study the stress and strain contours of the microjoints sealed by different underfill materials. It was found that the lifetime of microjoints was highly related to the Tg points of underfills, an interfacial fracture was observed within the microjoints sealed by a lower Tg underfill after temperature cycling because the tensile strength damaged the Sn depletion zone as heated.

Results for a New SOFC-Stack Design with Parallel-Connected Cells

The TU Clausthal and CUTEC institute have teamed up to design, build and test a new stack architecture, based on repeating units with cells connected in parallel. This approach allows the use of electrically conducting seals like brazes and can be realized without any glass sealing. Unlike conventional (serially connected) stacks, where all cells operate at the same current but individual voltage, in this setup each cell contributes as much current as possible at a common voltage. Thereby accelerated degeneration caused by undervoltage and the associated oxidation of the nickel catalyst can be completely overcome. The concept uses two cells in electrical parallel connection with the anodes facing each other to form a repeating unit. Two designs have been realized: An all ceramic housing made from 3YSZ, sealed with reactive air brazing (RAB) and a metallic one with a Crofer 22 APU housing, joined by laser beam welding. The housing materials have been chosen with respect to their thermal expansion coefficient (TEC) matching the TEC of the used ESC cells. Special interconnectors have been produced via hydroforming to create an even flow field while providing sufficient contact area. The paper will focus on the test results of the repeating units under various operation conditions and the analysis of the degradation of components and joints. Polarization curves for the twincell repeating unit and the individuell cells under H2 and air at 880°C are depicted in figure one. Figure 1

Results for a New SOFC-Stack Design with Parallel-Connected Cells

The TU Clausthal and CUTEC have teamed up to design, build and test a new SOFC stack architecture, based on repeating units with cells connected in parallel. This approach allows the use of electrically conducting seals like brazes and can be realized without any glass sealing. Unlike conventional (serially connected) stacks, where all cells operate at the same current but individual voltage, in this setup each cell contributes as much current as possible at a common voltage. Thereby accelerated degeneration caused by undervoltage and the associated oxidation of the nickel catalyst can be completely overcome. The concept uses two cells in electrical parallel connection with the anodes facing each other to form a repeating unit. Two designs have been realized: An all ceramic housing made from 3YSZ, sealed with reactive air brazing (RAB) and a metallic one with Crofer 22 APU housing, joined by laser beam welding.

Virtual RATs and a flexible and tailored radio access network evolving to 5G

This article first analyzes the requirements and challenges in the future 5G mobile wireless network. Then the authors describe a new method for radio access technologies called virtual RATs. The proposed scheme can provide a flexible and tailored access network that can meet the requirements and overcome the challenges in mobile broadband networks. The authors also present a high level design of the overall architecture and protocol stack for virtual RATs. Two concepts, virtual RAT Types and interface sets, are introduced. Two essential features, flexible control/user (C/U) plane separation and coordination between virtual RATs, are also discussed. Examples are provided to show how to achieve a flexible and tailored access network for services by using virtual RATs. Finally, the capability of hardware to support implementation of virtual RATs is analyzed.

Local Features and a Two-Layer Stacking Architecture for Semantic Concept Detection in Video

In this paper, we deal with the problem of extending and using different local descriptors, as well as exploiting concept correlations, toward improved video semantic concept detection. We examine how the state-of-the-art binary local descriptors can facilitate concept detection, we propose color extensions of them inspired by previously proposed color extensions of scale invariant feature transform, and we show that the latter color extension paradigm is generally applicable to both binary and nonbinary local descriptors. In order to use them in conjunction with a state-of-the-art feature encoding, we compact the above color extensions using PCA and we compare two alternatives for doing this. Concerning the learning stage of concept detection, we perform a comparative study and propose an improved way of employing stacked models, which capture concept correlations, using multilabel classification algorithms in the last layer of the stack. We examine and compare the effectiveness of the above algorithms in both semantic video indexing within a large video collection and in the somewhat different problem of individual video annotation with semantic concepts, on the extensive video data set of the 2013 TRECVID Semantic Indexing Task. Several conclusions are drawn from these experiments on how to improve the video semantic concept detection.

1D photonic defect structures based on colloidal porous frameworks: Reverse pore engineering and vapor sorption

Stimuli-responsive 1D photonic crystals, referred to as Bragg stacks, are capable of translating environmental changes into a color read-out through changes in the effective refractive index (RI) of the multilayer system upon infiltration with an analyte. The sensitivity and versatility of prototypic SiO2/TiO2 multilayers can be greatly enhanced by the use of nanoparticulate or mesoporous building blocks, or inherently microporous structures such as metal-organic frameworks (MOFs). Here, we introduce a stimuli-responsive ZIF-8 “defect” layer into SiO2/TiO2 multilayers in order to combine the high optical quality of a Bragg stack with the characteristic sorption properties of the MOF. The addition of a planar defect layer, either embedded in or deposited on top of the Bragg stack acts as a “dopant” and introduces a narrow band of allowed states in the photonic band gap, which can be utilized for the precise determination of the optical response of the Bragg stack. We demonstrate the impact of layer morphology, layer sequence and the position of the defect on the optical and vapor sorption properties of the photonic architectures. Moreover, a facile process is presented which allows for the clean inversion of the acid-sensitive ZIF-8 defect layer into a mesoporous layer in a one-step fashion, while the layer structure and optical quality of the stack architecture is preserved.

What entrepreneurs discover when creating opportunities? Insights from Skype and YouTube ventures

Although the scholarly conversation about how entrepreneurial opportunities emerge has suggested that entrepreneurs both discover and create opportunity components, specific knowledge about what components are discovered is lacking. In this research, we use an exploratory case study to investigate the opportunity creation process. We found that entrepreneurs discover several opportunity-related components based on the prior experience and knowledge of other entrepreneurs. Drawing on the evidence from these exploratory cases, we identify three important types of components that entrepreneurs creatively recombine within an emerging opportunity: technology stack, business model, and product and service design architecture. These findings have important implications for our understanding of entrepreneurial bricolage and entrepreneurial recycling, and their connection to the process of opportunity creation.