Spurious-free Dynamic Range Research Articles

Re-configurable digital bandwidth interleaved sampling system based on fast spectrum sensing.

The complexity of systems with parallel acquisition architectures has increased sharply with the continuous growth of signal bandwidth, and sampling precision has been greatly challenged. Considering that the signal to be measured usually exhibits sparsity in the frequency domain, this paper proposes a re-configurable bandwidth interleaved acquisition architecture to maximize test flexibility and accuracy. The sampling process is divided into two stages: sensing and re-configurable acquisition. In the sensing stage, the signal spectrum distribution is roughly understood using a sparse Fourier transform. Based on the spectrum sensing results, the subband selection and the adaptive adjustment of the mixing local oscillator in the acquisition system are performed. Ultimately, these steps enhance sampling accuracy. This paper verifies the effectiveness of this method on a 10GHz acquisition system, demonstrating that it can significantly reduce data redundancy. In addition, it improves acquisition accuracy compared to traditional bandwidth interleaved systems. The experimental results indicate that re-configurable sampling can significantly improve the quality of sampling results. This is evidenced by a signal-to-noise ratio improvement of over 7.4 dB and a spurious-free dynamic range improvement of over 4.7 dB compared to traditional sampling results.

Optimized Design of Direct Digital Frequency Synthesizer Based on Hermite Interpolation

To address the issue of suboptimal spectral purity in Direct Digital Frequency Synthesis (DDFS) within resource-constrained environments, this paper proposes an optimized DDFS technique based on cubic Hermite interpolation. Initially, a DDFS hardware architecture is implemented on a Field-Programmable Gate Array (FPGA); subsequently, essential interpolation parameters are extracted by combining the derivative relations of sine and cosine functions with a dual-port Read-Only Memory (ROM) structure using the cubic Hermite interpolation method to reconstruct high-fidelity target waveforms. This approach effectively mitigates spurious issues caused by amplitude quantization during the DDFS digitalization process while reducing data node storage units. Moreover, this paper introduces single-quadrant ROM compression technology to further diminish the required storage space. Experimental results indicate that, compared to traditional DDFS methods, the optimization scheme proposed in this work achieves a ROM resource compression ratio of 1792:1 and a 14-bit output Spurious-Free Dynamic Range (SFDR) of −88.134 dBc, effectively enhancing amplitude quantization precision and significantly lowering spurious levels. This significantly improves amplitude quantization precision and reduces spurious levels. The proposed scheme demonstrates notable advantages in both spectral performance and resource utilization efficiency, making it highly suitable for resource-constrained embedded systems and high-performance applications such as radar and communication systems.

A Microwave Photonic Channelized Receiver Based on Polarization-Division Multiplexing of Optical Signals

Aimed at the problems of optical frequency combs, such as their large number of comb lines, their high flatness, and their lack of ease in generating, as well as the fact that the channelization efficiency of the scheme based on optical frequency combs is low, we proposed a microwave photonic channelization receiver based on signal polarization multiplexing. Using two-line local optical frequency combs with different frequencies to demodulate the RF signal in the orthogonal polarization state, 16 sub-channels with a bandwidth of 1 GHz can be received simultaneously. The experimental results show that the image rejection ratio can reach 28 dB, and the third-order spurious-free dynamic range of the system can reach 96.8 dB·Hz2∕3. This scheme has the advantages of a large number of sub-channels and a high channelization efficiency; it has great application potential in broadband wireless communication, radar, and electronic warfare systems.

A Calibration Scheme for a 800-Ms/s 14 Bit Pipelined ADC in 28-nm CMOS

Abstract A calibration scheme is proposed to compensate linear and nonlinear errors including offset, cap mismatch, second- and higher-order harmonics and memory induced errors in pipelined analog-to-digital converters (ADCs). The alternating minimization (AM) algorithm is proposed to accurately estimate the coefficients of the errors. As an accurate input value is hardly acquired in practical measurements, instead, the proposed scheme estimates the input and the error coefficients jointly. Once the error coefficient was calculated, it will be recorded in a lookup table (LUT). The scheme has been demonstrated in a 800-Ms/s 14-bit pipelined ADC fabricated in a 28nm CMOS process, which features a signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) improvement of 2.49 dB and 11.49 dB at 800-Ms/s.

An all-digital low-complexity blind background calibration of timing mismatch in time-interleaved ADCs

This paper proposed a novel all-digital blind background calibration to mitigate timing mismatch in time-interleaved analog-to-digital converter (TIADC). In estimation module, the adoption of a subtraction-based error extraction function and the design of Variable-Step-Size Least Mean Squares algorithm contribute to reducing the computational complexity and enhancing the convergence speed with optimal output accuracy respectively. In compensation module, a dual-stage Taylor series expansion structure has been introduced to effectively maintain the overall output performance. The proposed architecture is applied to a 12-bit 3 GS/s four-channel TIADC model. Its effectiveness for single-tone and multi-tone signals is proven through systematical testing and analysis. The simulation results exhibit that the Spurious Free Dynamic Range is significantly improved by 54.53 dB in the single-tone signal case, and the timing mismatch is converged after 1000 samples. The proposed calibration circuit has been synthesized utilizing a 28 nm standard cell library for assessing its hardware consumption, area (0.051 mm2) and average power dissipation (67.5 mW) within the integrated chip architecture. Our technology provides a viable optimization solution to improve efficiency of TIADC in high-speed systems.

A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC

A foreground calibration is proposed to obtain the real weights in the split capacitor digital-to-analog- converter (CDAC) of a 14-bit 1-MS/s successive-approximation-register (SAR) ADC. Since the non-linearity of high-resolution SAR ADC is mainly caused by the mismatch of capacitors, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By injecting a multi-level dither signal in both the calibration and conversion phases of the calibration scheme, the precision and non-linearity of SAR ADC can be significantly improved. Simulation results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 79.93 dB and 91.21 dB by employing the proposed calibration technique in a 14-bit split-CDAC SAR ADC. Besides, integral non-linearity (INL) achieves 0.22 least-significant bit (LSB).

Genetic neural network based background calibration method for pipeline ADC

This article presents a pipeline analog-to-digital converter (ADC) background calibration method that combines genetic algorithm (GA) and neural network (NN) algorithm. The proposed method uses ADC outputs or individual stage sub-ADC outputs for NN training, employs GA for global optimization of the NN's initial setup to avoid local optima traps, and utilizes a parallel pipeline architecture to create a high-throughput calibration circuit with optimized multiply-accumulator (MAC) to minimize resource consumption. Through simulation on a 6-stage 14-bit pipelined ADC model, the proposed method demonstrated superiority over traditional calibration techniques and other NN-based calibration strategies. Specifically, after calibration, the signal-to-noise ratio (SNDR), spurious-free dynamic range (SFDR), and effective number of bits (ENOB) are significantly improved from 57.72 dB, 59.77 dB, and 8.79 bits to 104.61 dB, 152.64 dB, and 17.08 bits, respectively.

Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages.

A Fast and Cost-Effective Calibration Strategy of Inter-Stage Residual Amplification Errors for Cyclic-Pipelined ADCs

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm2.

Performance study of microwave photonic links by considering the effect of phase shifters and bias conditions on dual-drive dual parallel Mach–Zehnder modulator

Abstract This paper presents the performance analysis of different schemes for generating linearized photonic signal by varying phase shifter arrangements of a dual-drive dual parallel Mach–Zehnder modulator (DD-DPMZM). The RF signals at the electrodes of sub-modulators of DD-DPMZM are fed using different phase angles to generate optically modulated signals in the output. The proposed system consists of a DD-DPMZM and phase shifters. Spurious free dynamic range (SFDR) is evaluated for different configurations of sub modulators in upper and lower arm of DD-DPMZM. SFDR of 135.6 dB Hz4/5 is obtained for quadrature and optical carrier suppression modulation in upper and lower submodulators by suppressing third order intermodulation distortion completely. It is found to be high performance configuration for dual parallel Mach–Zehnder modulator based linear microwave photonic link.

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

Design and Implementation of Digital Down Converter for WiFi Network

This paper introduces a field-programmable gate array (FPGA)-based digital down converter (DDC) processing a sampling frequency of about 3.64 GHz to a down-converted frequency of 28.4375 MHz to match the IEEE 802.11ah Wi-Fi HaLow standard. The proposed DDC uses a polyphase mixer(PM) and a resampling filter. The PM adopts parallel coordinate rotation digital computer (CORDIC) processors and lowpass filter arrays to reduce high-speed data rates with minimum resource utilization. Again, the resampling filter employs a cascaded integrator comb (CIC) filter associated with a parallel prefixed adder (PPA) and a multi-channel systolic finite impulse response (FIR) filter implemented with canonical expression, attaining optimum hardware cost. Converting floating-point to fixed-point data types provides significant resource savings. Finally, the improved design is coded in the Xilinx Vivado synthesis tool and successfully tested on the FPGA Kintex-7 device. In contrast to other recent architectures, the proposed design substantially reduces area requirements and power utilization. The Matlab tool verifies the design to achieve an acceptable spurious-free dynamic range (SFDR) of 115 dB.

Hadamard transformation based frequency response mismatch calibration for a 4-channel TIADC

The time-interleaved analog-to-digital converter (TIADC) is one of the most effective solutions for improving the sampling rate of acquisition systems. However, the frequency response mismatch between channels can seriously degrade the performance of the system. In this paper, we propose a calibration method for frequency response mismatches in 4-channel TIADC systems. Following the construction of a four-channel TIADC model using a four-order Hadamard matrix, the error signals were extracted using three time-invariant filters and subsequently subtracted from the output to complete the calibration. It uses the Hadamard transform instead of the complex exponential modulator used in conventional time-varying filter methods, which can further simplify the signal processing without the necessity of complicated calculations. We have employed a stimulated four-channel TIADC system to validate the effectiveness of the proposed calibration technique. Moreover, in a commercial 12.5 GSPS four-channel TIADC system, it is also demonstrated that this approach is effective in improving the spurious-free dynamic range of the system.

Superconducting electronic device response linearity calculation method using discrete fourier analysis

A highly effective method of the device linearity calculation on the stage of the device development is worked out and reported. The method allows expressing the linearity in terms of the achievable spurious-free dynamic range (SFDR) of the created devices, in particular superconductive electronic devices, and therefore can be easy correlated with the obtained experimental data. The algorithm scheme and the method accuracy are considered and discussed in detail.

Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters

SummaryA new mechanism of digital background calibration in pipeline analog‐to‐digital converters (ADCs) is expressed. The presented technique calibrates various errors like capacitor mismatch, finite DC gain of the amplifier, third‐order nonlinearity, and fifth‐order nonlinearity, so it is called multipurpose. In this method, the error coefficients are identified by estimation of the output code of the decision points in the voltage transfer characteristic (VTC) of the pipeline stages. To achieve sufficient decision points in the VTCs of the pipeline stages, one threshold level of one comparator of the sub‐ADC is shifted, and then the digital output is calibrated by capturing the error coefficients. The digital logic of this method is simple and does not require special analog circuits. The introduced calibration mechanism is evaluated for the first five stages of a 12‐bit 100 MS/s pipeline ADC. The required time for the calibration is 1.5 ms. By applying this method, the signal‐to‐noise and distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) in order are enhanced from 46.44 and 50.53 dB to 69.92 and 74.04 dB, respectively.

A neural network‐based error correction in the first‐stage residue of pipelined analog to digital converters

SummaryAn analog background calibration approach is presented for the full calibration of pipeline analog‐to‐digital converters (ADCs). A well‐trained neural network acts close to the ideal 1.5‐bit stage, and its residue is compared with the real 1.5‐bit stage including gain error and amplifier nonlinearities. The detected error is used to compensate for the imperfect residue using four calibration polynomial coefficients. The corrected residue enters the second stage of the pipeline ADC and follows a normal path to achieve high resolution. The introduced structure is verified in a 12‐bit pipelined ADC composed of 11 stages; the first 10 stages have a 1.5‐bit structure, while the last stage is a 2‐bit flash. The sampling frequency is 100 MHz, and 10% non‐ideal factors (5% for each of the nonlinear and gain errors and 10% for the aggregated error) are considered for the first stage, while the input is 19.5 MHz sinusoidal waveform. A random noise is applied to the input to limit the effective number of bits (ENOB) to almost 11.8. The evaluation parameters of the ADC are extracted, signal‐to‐noise and distortion ratio increases from 39.14 to 72.91 dB, spurious free dynamic range improves from 40.94 to 79.69 dB, and the ENOB enhances from 6.2 to 11.82. The presented mechanism shows an acceptable accuracy in the high‐speed and high‐resolution ADCs.

Transmit-isolating photonic receivers with high isolation, large dynamic range based on reverse single-sideband modulation

Two kinds of transmit-isolating photonic receiver (TIPRx) systems with high isolation, large dynamic range based on reverse single-sideband (SSB) modulation are proposed and demonstrated. For the single dual-drive modulator (DD-MZM), the transmit signal allows less leakage of the RF power to the PD compared with the reverse double-sideband (DSB) modulation, thanks to the reduction in the number of the sidebands beating with the center carrier, while the forward DSB modulation benefits the high-quality response of the receive signal. Experimental results demonstrate that the average isolation is increased by 3–4 dB through suppressing the sideband intensity of the counter-propagation modulation, and the system has an isolation greater than 15 dB within 4–24 GHz. In addition, the spurious-free dynamic range (SFDR) of 98.31 dB·HZ2/3 is achieved. The parallel DD-MZMs scheme is put forward to improve the isolation and SFDR simultaneously, through the accurate cancellation of the reverse sidebands and third-order intermodulation (IMD3) components. The simulation result proves that the parallel architecture can suppress the reverse response and IMD3 effectively, and has the null of 0.10 for the isolation and the null of 0.20 for the IMD3 components when the optical power ratio is 0.9. The proposed technique can find applications in analog and digital communication.

Broadband photoelectric fusion transceiver-multiplexed conversion system with high spurious rejection

In this paper, a broadband photoelectric fusion transceiver-multiplexed system is proposed to realize a frequency converter. The system achieves a high spurious suppression ratio through two frequency conversions that utilize the advantages of microwave and photonics technology simultaneously to reduce the complexity of the system and improve the effective spectrum utilization. In addition, the core components, such as the Mach–Zehnder modulator (MZM), are multiplexed in the up and down frequency conversion link. High-frequency local oscillator (LO) signals are used to keep image frequency signals and various kinds of spurious signals obtained by beating frequency outside the system bandwidth. Experimental results demonstrate that the operating frequency ranges from 2 to 18 GHz with high performance for both transmitter and receiver. The image rejection is 57.35 dB for up-conversion and 46.56 dB for down-conversion, and the in-band spurious suppression achieves at least 55.02 dB. At the same time, the spurious-free dynamic range (SFDR) can reach at least 89.11dB⋅Hz2/3.

A Novel Bootstrapped CMOS Switch with Minimized Sampling and Holding Error Using Sampling Window Error Analysis

This study proposes a novel 6-transistor bootstrapped switch with minimized sampling and holding error obtained through sampling window error analysis for SAR ADC design. The proposed switch design strategically mitigates channel charge injection and minimizes the input signal dependency of on-resistance by optimizing its sizing parameters. To counteract channel charge effects, dummy NMOS and PMOS components are judiciously employed, culminating in a substantial improvement in the effective number of bits (ENOB). The complete analysis of the proposed circuit is done using the Cadence Virtuoso SCL 0.18[Formula: see text][Formula: see text]m CMOS process. For a 51.514[Formula: see text]kHz sinusoidal 1[Formula: see text]V peak-to-peak differential input signal with a 1[Formula: see text]MSPs clock speed, the proposed circuit achieves 2.0141[Formula: see text]mV maximum sampling window error, 0.131[Formula: see text][Formula: see text]W power consumption, 84.67 dB signal-to-noise ratio (SNR), 84.67 signal-to-noise and distortion (SINAD) ratio and 86.02 dB spurious-free dynamic range (SFDR), which produces 13.77 bits ENOB. For the impacts of process variations and mismatch on switch performance, a comprehensive 500-point Monte Carlo (MC) simulation of the proposed bootstrap switch is conducted in this study. Post-layout results show that the proposed circuit is suitable for IoT applications.

A 12-Bit 1.2-GS/s Current-Steering DAC in 45-NM CMOS Technology

This research paper presents a 12-bit 8–4-segmented current-steering DAC (digital-to-analog converter) that offers notable advantages, particularly in terms of its reduced power consumption compared to other similar designs. The exceptional performance of our DAC can be attributed to two key factors: the use of a thermometer encoder and an efficient digital input bit segmentation. These features contribute to enhanced precision and reduced power requirements, setting our DAC apart from the existing solutions in the field. These enhancements significantly reduce glitches and improve the accuracy of the DAC’s output. DAC dissipates a total power of about 44.95[Formula: see text]mW when running at a sample rate of 1.2[Formula: see text]GHz with the CMOS technology of 45[Formula: see text]nm. While the supply input voltage is held constant at 1.2[Formula: see text]V, the DAC’s digital input is pulsating in nature in which the ON voltage is 1[Formula: see text]V and OFF voltage is 0[Formula: see text]V. Also, the DAC has a spurious-free dynamic range (SFDR) of 41.77[Formula: see text]dB.