Spurious-free Dynamic Range Research Articles

A glitch energy reduction method with low complexity dynamic element matching for data converters

Due to the appearance of huge glitch while using traditional Dynamic Element Matching (DEM) in data converters, different kinds of glitch-reduce structures are designed into DEM. However, most of these structures will work with high complexity. Based on random-rotation-binary-weighted selection (RRBS), this paper presents a novel low complexity glitch-reduced DEM algorithm, which can greatly reduce mismatch. The proposed DEM constructs glitch-reduce structure through data selector and comparator, so the complexity is reduced through using less components. As a result, the glitch-reduced DEM increases spurious free dynamic range (SFDR) to 92.47dB at 7.6MHz. Moreover, compared with conventional RRBS, glitch-reduced DEM makes the glitch reduce by 49% with low complexity in a 12-bit digital-to-analog converter (DAC).

A Digital Timing-Mismatch Calibration Technique for Time-Interleaved ADCs Based on a Coordinate Rotational Digital Computer Algorithm

Timing-mismatch errors among channels in time-interleaved analog-to-digital converters (TIADCs) greatly degrade the whole performance of the system. Therefore, techniques for calibrating timing mismatch are indispensable, and a new fully-digital calibration technique is presented in this article. Based on a Hilbert filter, modified moving averagers (MMAs) and inverse cosine functions, the proposed estimation algorithm is fast (within 1200 sample points) and accurate. Meanwhile, the coordinate rotational digital computer (CORDIC) algorithm, which is used to implement inverse cosine functions, is also improved, giving it higher precision. In addition, a compensation method based on second-order Taylor series approximation with less hardware resource consumption is provided. Through analyses and simulations, this calibration technique proved to be suitable for TIADCs with an arbitrary number of channels, in which the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were, respectively, improved from 24.06 dB and 24.57 dB to 67.96 dB and 85.69 dB.

A Multiple Interpolation Algorithm to Improve Resampling Accuracy in Data Triggers

To address the problem of low trigger accuracy during trigger resampling and variable sampling rate trigger resampling using a fixed sampling rate analog-to-digital converter (ADC), this paper proposes an interpolation method combining sinc interpolation and linear interpolation to improve accuracy, based on a digital trigger. After behavior simulation verification and actual field programmable gate array (FPGA) test verification, the data collected by two 3GSps 12-bit ADCs were subjected to 8-times sinc interpolation followed by 16-times linear interpolation processing, after which the original trigger resampling accuracy was increased by 128 times and the sampling rate could be realized to vary between 100 MHz and 1 GHz. A signal–noise ratio (SNR) of 46.80 dBFS, a spurious free dynamic range (SFDR) of 45.91 dB, and an effective number of bits (ENOB) of 7.48 bits were obtained by direct trigger resampling without algorithm processing in the behavior simulation. Meanwhile, an SNR of 58.98 dBFS, an SFDR of 60.96 dB, and an ENOB of 9.42 bits were obtained by trigger resampling after algorithm processing. Due to the influence of analog link signal loss and signal interference on the development board, an SNR, SFDR and ENOB of 51.97 dBFS, 61.26 dB, and 8.32 bits, respectively, were obtained from the trigger resampling in the FPGA test. The experimental results show that the algorithm has not only improved the triggering accuracy but has also improved the SNR, SFDR, and ENOB parameters.

On-Chip Fast Signal Generation and Low-Power SAR ADC for SiPM Readout

This article presents an ON-chip fast signal generator and a successive-approximation-register (SAR) analog-to-digital data converter (ADC) for silicon photomultiplier (SiPM) readout applications. The high-pass filter (HPF)-based fast-signal generator sharpens the rising edge of the standard SiPM output signal reducing time jitter due to the dark counts of the detector. It is implemented by leveraging the equivalent resistance of the current mirror transistor and the ac-coupling capacitor between the current mirror and the current discriminator to avoid hardware and power consumption overhead. Compared with OFF-chip solutions, the ON-chip approach eliminates the packaging pins and high-speed buffers needed for carrying the fast signals reducing packaging complexity and power consumption of the readout system. The energy quantizer utilizes the SiPM charge integrator as the ADC track-and-hold (T/H) circuit to improve the front-end power efficiency. The fast signal generator and the SAR ADC are implemented in a current-mode application-specific integrated circuit (ASIC) designed in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. Measurement results show that the ON-chip fast signal generator is effective in improving the timing performance of the readout system. The timing resolutions are measured using SensL’s <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> 3 mm2 SiPM device with a terminal capacitance of 850 pF using an ultrashort laser pulser. Measurement results show that the fast signal generator improves the timing resolution by 23.4% compared with timing measurement using the standard output signal when the output charge is 300 pC. The ASIC achieved a measured ADC signal-to-noise-distortion ratio (SNDR) of 53.08 dB and a spurious-free dynamic range (SFDR) of 62.74 dB at 1 MS/s and a maximum front-end gain nonlinearity of 3.3% over 20–800-pC input charge range while dissipating 4.1 mW of power from a 1.8-V supply.

Fully Digital Calibration Technique for Channel Mismatch of TIADC at Any Frequency

This paper presents a fully digital modulation calibration technique for channel mismatch of TIADC at any frequency. By pre-inputting a test signal in TIADC, the mismatch errors are estimated and stored, and the stored values will be extracted for compensation when the input signal is at special frequency which can be detected by a threshold judgement module, thus solving the problem that the traditional modulation calibration algorithm cannot calibrate the signal at special frequency. Then, by adjusting the operation order among the error estimation coefficient, modulation function and input signal in the calibration loop, further, the order of correlation and modulation in the error estimation module, the complexity of the proposed calibration algorithm is greatly reduced and it will not increase with the number of channels of TIADC. What's more, the hardware consumption of filters in calibration algorithm is greatly reduced by introducing a CSD (Canonical Signed Digit) coding technique based on Horner's rule and sub-expression sharing. Applied to a four-channel 14bit 560MHz TIADC system, with input signal at 75.6MHz, the FPGA verification results show that, after calibration, the spurious-free dynamic range (SFDR) improves from 33.47dB to 99.81dB and signal-to-noise distortion ratio (SNDR) increases from 30.15dB to 81.89dB.

A Design of All-Optical Integrated Linearized Modulator Based on Asymmetric Mach-Zehnder Modulator

We proposed an all-optical linearized modulator model suitable for an integration platform. The linearized modulator is formed by an asymmetric Mach–Zehnder modulator and a carrier-separated waveguide. We focus on the suppression of both intermodulation distortion (IMD3) and second-order harmonic distortions (SHD). As a result, the third-order nonlinear terms of IMD3 and second-order nonlinear terms of SHD are entirely suppressed, leading to a spurious free dynamic range of IMD3 (SFDRIMD3) improvement of ~14 dB and SFDRSHD improvement of ~3 dB compared with a standard MZM model. The influence of large RF input signals, losses, and fabrication deviations are also discussed to prove the feasibility of the model.

A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process

This paper presents a 1-GS/s12-bit pipelined analog-to-digital converter (ADC) fabricated in 40-nm CMOS technology that optimizes the settling time, bit error rate, and robustness. This ADC uses an improved timing called pre-quantization timing (PQT), which implements quantization in half the time of the sampling phase to maximize the output-settling time of the operational amplifier (op-amp). A complete clocking scheme along with a delay lock loop (DLL) is proposed to generate an accurate timing no matter how process, voltage, and temperature (PVT) change. Based on PQT, a high-speed comparator circuit is adopted to obtain a bit error rate (BER) below 10−15. Sample and hold amplifier (SHA) is used to guarantee robustness over the wide input frequency. Furthermore, a low-cost automatic calibration is implemented to correct residual curves, and inter-stage gain errors are also corrected. This ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.3 dB and a spurious-free dynamic range (SFDR) of 78.5 dB at a 227 MHz input frequency. The measured differential nonlinearities (DNL) and integral nonlinearities (INL) after calibration are ±0.7 LSB and ±1.50 LSB, respectively. The power consumption of the ADC core is 97.6-mW, and the Walden figure of merit (FoM) is 172.9-fJ/conversion-step.

Improvement of linearity in intensity-modulated analog photonic link based on all-optical wave shaping

In this paper, a novel all-optical architecture for multi-order nonlinear distortions (NDs) suppression in the intensity-modulation direct-detection (IM-DD) analog photonic link (APL) is proposed. A systematic analysis of the relationship between the NDs and all optical sidebands (OSBs) is summarized. Numerical simulation results show that, by optimizing the amplitude and phase of OSB, the 3rd-order intermodulation distortion (IMD3) can be significantly suppressed. Consequently, the spurious-free dynamic range (SFDR) of 107.1 dBHz8/9 is obtained, which is improved by 16.17 dB compared with a single quadrature biased Mach–Zehnder modulator (MZM) used in APL.

Performance Analysis on Interference and Frequency-to-Time Mapping Based Frequency Hopping Receiver

The receiving performance of a frequency hopping receiver based on interference and frequency-to-time mapping are analyzed. The broadening of the receiving passband induced by high frequency hopping speed is theoretically analyzed. The spurious-free dynamic range (SFDR), the frequency-dependent RF gain, and the average signal-to-noise ratio (SNR) corresponding to the RF gain are theoretically derived to indicate the receiving performance. Experimental verifications on the SFDR and RF gain were conducted. The SFDR of the passband at 7.21 GHz is 77.23 dBc, and for the passbands located from 7 GHz to 23 GHz, the SFDR variance is below 3.2 dB, which fits well with the simulated results with the difference of less than 3.7 dB. The RF gain for passbands located from 2.6 GHz to 40.9 GHz were tested, and the difference is less than 2 dB compared to the theoretical results.

A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration

Time interleaving (TI) is an effective approach to higher speed conversion of current-steering digital-to-analog converters (DACs). However, achieving high linearity performance for these TI DACs is challenging during interleaving synchronization, output current summation, and parasitic capacitance control. This article exploits the design of a 6.0-GS/s 14-bit two-channel time-interleaved DAC in a 65-nm CMOS process for communication systems. A novel asymmetric current-tree summation network is proposed to reduce the current summation nonlinearity in the DAC. A differential clock phase and duty-cycle calibration scheme is also adopted while achieving low complexity. Furthermore, a current source layout optimization scheme is proposed that significantly reduces the parasitic capacitance of interleaving switches and improves the linearity. Measurement results of the fabricated DAC show 6–20-dB spurious-free dynamic range (SFDR) improvement with the proposed techniques, achieving >60-dB SFDR up to 1355 MHz and >50-dB SFDR up to the Nyquist.

A 120 MHz fast automatic tuning CMOS active-RC lowpass filter

In this paper, a fast automatic cutoff frequency calibrating, CMOS lowpass filter with linear-in-dB tunable gain and constant in-band group delay is presented. The automatic frequency tuning (AFT) circuit can successfully tune the cutoff frequency to 120 MHz with less than 4.7% error. In-band group delay variation is handled using a capacitor process variation detection circuit (CPVD), and the overall tuning time is less than 700 ns. The design is done using STM PD-SOI 130 nm CMOS process, and the supply voltage is 1.2 V with a total power consumption of 21.7 mW. The overall filter provides a programmable linear-in-dB gain of 0.5 dB to 17.6 dB range with a cutoff tuning range of 80 to 180 MHz. The in-band group delay variation is below 500 ps with an adjacent channel ratio (ACR) of 85 dB. The spurious free dynamic range (SFDR) is over 66.6 dBc. The active area of the filter with tuning is 0.171 mm2.

A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction

This article presents a 60-MS/s 5-MHz BW noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an integrated highly linear input buffer in a 40-nm CMOS process. A dynamic level-shifting (DLS) technique is proposed to adaptively adjust the output common-mode voltage of the integrated input buffer for different operation phases, achieving the optimal linearity while alleviating the voltage breakdown problem at the capacitive digital-to-analog converter (CDAC) top plate. The mismatch-error-shaping (MES) technique is utilized to minimize the CDAC mismatch, which also generates undesired inter-symbol-interference (ISI) errors as a side effect. An ISI-error correction (IEC) technique is proposed to mitigate this problem and further improve the linearity. Both foreground and background calibrations are adopted in the subranging ADC and the NS filter to improve the gain accuracy. This SAR ADC prototype, with an integrated input buffer driving a 4.4-pF CDAC within 2.7 ns, achieves signal-to-noise ratio (SNR)/signal-to-noise-and-distortion ratio (SNDR)/spurious-free dynamic range (SFDR)/dynamic range (DR)/total harmonic distortion (THD) of 85.4 dB/84.2 dB/97.3 dBc/86.4 dB/−92.9 dBc while consuming 8.06 mW from 2.5- and 1.1-V dual supply voltages. The Walden FoM (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {W}}$ </tex-math></inline-formula> ) and figure-of-merit (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {S}}$ </tex-math></inline-formula> ) are 60.6 fJ/conv.-step and 172.1 dB, respectively.

A New Noise Shaping Approach for Sigma-Delta Modulators Using Two-Stage Feed-Forward Delays and Hybrid MASH-EFM

Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved.

High-Performance Microwave Photonic Transmission Enabled by an Adapter for Fundamental Mode in MMFs

Microwave photonic links (MPLs) have long been considered as an excellent way for radio frequency (RF) transmission due to their advantages such as light weight, high bandwidth, low cost and large spurious-free dynamic range (SFDR). However, the effective mode-field area (Aeff) of the single-mode fiber (SMF) used in the traditional MPL is not large, so the MPL based on SMF have relatively strong nonlinearity, which limits the processing power of SMFs to a level of few milliwatts. Few-mode fibers (FMFs) have been applied in MPL as an alternative due to the larger Aeff, and photonic lanterns are used simultaneously to excite the high-order mode of FMFs for RF signal transmission. However, the photonic lantern could bring additional insertion loss, and the production cost of FMFs is high, so we propose an MPL based on multimode fibers (MMFs) with mode field adapters (MFAs). Since MMFs have larger Aeff, the nonlinearity of the link can be greatly reduced. And matched MFAs realized by reverse tapering, to excite only the fundamental mode in MMFs to reduce the crosstalk, which are very stable. As a result, the stimulated Brillouin scattering threshold and SFDR are improved by 5 dB and 14.5 dB, respectively.

Multiband Signal Receiver by Using an Optical Bandpass Filter Integrated with a Photodetector on a Chip

Photonic integration brings the promise of significant cost, power and space savings and propels the real applications of microwave photonic technology. In this paper, a multiband radio frequency (RF) signal simultaneous receiver using an optical bandpass filter (OBPF) integrated with a photodetector (PD) on a chip is proposed, which was experimentally demonstrated. The OBPF was composed of ring-assisted Mach-Zehnder interferometer with a periodical bandpass response featuring a box-like spectral shape. The OBPF was connected to a PD and then integrated onto a single silicon photonic chip. Phase-modulated multiband RF signals transmitted from different locations were inputted into the OBPF, by which one RF sideband was filtered out and the phase modulation to intensity modulation conversion was realized. The single sideband with carrier signals were then simultaneously detected by the PD. A proof-of-concept experiment with the silicon photonic integrated chip was implemented to simultaneously receive four channels of 8 GHz, 12 GHz, 14 GHz and 18 GHz in the X- and Ku-bands. The performance of the integrated microwave photonic multiband receiver-including the receiving sensitivity, the spurious free dynamic range, the gain and the noise figure across the whole operation frequency band-was characterized in detail.

Broadband Microwave Photonic Channelizer with 18 Channels Based on Acousto-Optic Frequency Shifter

A microwave photonic channelizer can achieve instantaneous reception of ultra-wideband signals and effectively avoid electronic bottleneck; therefore, it can be perfectly applied to a wideband radar system and electronic warfare. In channelization schemes based on an optical frequency comb (OFC), the number of comb lines usually depends on that of the sub-channels. In order to improve the utilization rate of the comb lines of OFC, we propose a scheme to shift the frequency of OFC by using an acousto-optic frequency shifter (AOFS), which can obtain three times the number of sub-channels of the comb lines of an OFC. In order to simplify the experiment, only a three-line OFC is used in the experiment. A three-line local oscillator (LO) OFC is frequency-shifted up and down by two AOFSs, and nine optical LO signals with different frequencies are obtained, thereby realizing the simultaneous reception of eighteen sub-channels. The proposed scheme enjoys a large number of sub-channels and minimal channel crosstalk. Experimental results demonstrate that a 9-GHz bandwidth RF signal covering 10–19 GHz is divided into 18 sub-channels with a sub-bandwidth of 500 MHz. The image rejection ratio of the sub-channels is about 23 dB, and the spurious-free dynamic range (SFDR) of the receiver can reach 98 dB·Hz2/3.

A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation

This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply.

A complementary high linearity bootstrap switch based on negative voltage bootstrap capacitor

The sample-and-hold (S/H) circuit is an important part of the analog-to-digital converter (ADC). A bootstrap switch with capacitive load can form a basic S/H circuit. A complementary high linearity gate voltage bootstrap switch based on bootstrap capacitor is proposed in this paper. By reducing the size of the key node transistors, the parasitic capacitance is reduced. The sampling metal-oxide-semiconductor field-effect transistor (MOSFET) in this structure is composed of complementary NMOS and PMOS, which reduces the channel charge injection effect and variations in on-resistance (Ron). The simulation results show that the effective number of bits (ENOB), signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the structure are 16.5 bits, 101.11 dB and 101.83 dB respectively at the sampling frequency of 50 MHz and full swing voltage input of 1.8 V based on SMIC 0.18 μm process. Compared with the conventional NMOS switch, ENOB, SDNR, and SFDR are increased by 2.45 bits, 14.73 dB, and 13.38 dB, respectively. In addition, Monte Carlo (MC) and corner simulations of the proposed circuit are performed, and the results show that the proposed circuit has good performance.

Ku-band analog photonic down-conversion link with coherent I/Q image rejection and digital linearization.

Analog photonic down-conversion links have been widely used in radar, electronic warfare, and satellite communication systems. Aiming at the optimization demands of the link performance, we demonstrate and experimentally verify a Ku-band photonic down-conversion link based on coherent in-phase/quadrature (I/Q) image rejection and digital nonlinear compensation. The image-rejection ratio at 17.5 GHz is measured to be 47 dB. After digital processing, the image intermodulation distortions (MMD) and the intermodulation distortions (IMD3) are suppressed by 18.1 dB and 10.9 dB, respectively. The corresponding spurious-free dynamic range (SFDR) reaches 108.83 dB·Hz2/3.

Speech Separation Methodology for Hearing Aid

In the design of hearing aids (HA), the real-time speech-enhancement is done. The digital hearing aids should provide high signal-to-noise ratio, gain improvement and should eliminate feedback. In generic hearing aids the performance towards different frequencies varies and non uniform. Existing noise cancellation and speech separation methods drops the voice magnitude under the noise environment. The performance of the HA for frequency response is non uniform. Existing noise suppression methods reduce the required signal strength also. So, the performance of uniform sub band analysis is poor when hearing aid is concern. In this paper, a speech separation method using Non-negative Matrix Factorization (NMF) algorithm is proposed for wavelet decomposition. The Proposed non-uniform filter-bank was validated by parameters like band power, Signal-to-noise ratio (SNR), Mean Square Error (MSE), Signal to Noise and Distortion Ratio (SINAD), Spurious-free dynamic range (SFDR), error and time. The speech recordings before and after separation was evaluated for quality using objective speech quality measures International Telecommunication Union -Telecommunication standard ITU-T P.862.