Spread Spectrum Clock Research Articles

A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation

A new technique utilizing two-point (TP) modulation for a spread spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a digital SigmaDelta modulator, and the voltage-controlled oscillator is modulated analogically. With this technique, the modulation bandwidth is enhanced in order that the modulation profile accuracy and jitter performance caused by the SigmaDelta modulator can be improved at the same time. The order of the SigmaDelta modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies specifications. The dual-path loop filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18 mum CMOS process. The size of the chip area is 0.44 times 0.48 mm2. The circuit produces a clock of 1.5 GHz with a down-modulation ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter, and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.

A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> ) and charge-pump (CP) current over C (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> /C), the SSCG can realize not only adaptive bandwidth but also process independence at each operating frequency. The innovative point is the adaptive bandwidth control using K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> /C calibration. This control enabled a test chip to keep a sharp triangular SSC profile while operating over a wide frequency range (125 to 1250 MHz). The variations of VCO gain and CP current are reduced to one third those of the conventional architecture. At 1250 Mbps (625 MHz) the reduction of spectrum peak amplitude is 18.6 dB which is 2.3 dB better than the reduction obtained without calibration.

EMI Reduction by Spread-Spectrum Clocking in Digitally-Controlled DC-DC Converters

SUMMARY This paper proposes spread-spectrum clock modulationalgorithms for EMI reduction in digitally-controlled DC-DC converters.In switching regulators using PWM, switching noise and harmonic noiseconcentrated in a narrow spectrum around the switching frequency cancause severe EMI. Spread-spectrum clock modulation can be used to min-imize EMI. In conventional switching regulators using analog control it isvery difficult to realize complex spread-spectrum clocking, however thispaper shows that it is relatively easy to implement spread-spectrum EMI-reduction using digital control. The proposed algorithm was verified usinga power converter simulator (SCAT). key words: PWM control, spread-spectrum clock modulation, EMI,digitally-controlled DC-DC converter 1. Introduction Most portable electronic devices have low-voltage high-current power supplies using high-efficiency switching reg-ulators. However, the considerable switching noise (andEMI) that switching regulators produce is a big demerit.EMI-related regulations are becoming more severe [1]. Reg-ulations prescribe limits on the generation of Electromag-netic Interference (EMI) and also noise-tolerance or Elec-tromagnetic Susceptibility (EMS) requirements; the combi-nation of both EMI and EMS is called EMC (Electromag-netic Compatibility). In many countries it is illegal to sellelectrical and electronic devices that do not comply with lo-cal EMC standards (in many cases devices must be type-approved, or tested and certified as complying). In mostconventional switching regulators, shielding and filteringare used to reduce EMI. While shielding and filtering areeffective ways of reducing noise, penalties associated withthis approach include the cost of transformers and coils andthe size/weight of shielding.We considered, as an alternative to extensive shield-ing and filtering, how to reduce EMI by switching regu-lator control-module design changes. After examining thepossible application of digital control systems with spread-spectrum technology [2]–[5] to analog-controlled switching

A $\Delta{-}\Sigma$ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology

A triangular-modulated spread-spectrum clock generator using a Delta-Sigma-modulated fractional-N phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased Delta-Sigma operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of plusmn0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies 950 times 850 mum2 in 0.18-mum CMOS process and consumes 36 mW.

Spread spectrum clock generator with hybrid controlled oscillator

A spread spectrum clock generator (SSCG) with a hybrid controlled oscillator (HCO) is presented. By using the proposed HCO, the modulation ratio of an SSCG can be made insensitive to process, voltage and temperature variations without a SigmaDelta fractional-N phase-locked loop. The simulated modulation ratio sensitivities are as low as - 1.3%/100degC and 7.0%/V for temperature and V DD , respectively. The SSCG IC, designed in a 0.18 m 1P4M CMOS process, operates from 40 to 90 MHz and consumes 5.5 mA from a 1.8 V supply voltage.

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics

This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction (-19 dB to the non-SSC situation) and a small core area of 0.25 mm2 in 0.13-mum CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm2. Moreover, it achieved good jitter tolerance (flat 0.8 UI at >1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m.

A 4–6.4 GHz LC PLL With Adaptive Bandwidth Control for a Forwarded Clock Link

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A wide range differentially tuned LC PLL using dual switched capacitor VCOs was designed in a 65 nm standard CMOS process for a forwarded clock link. Bandwidth and stability were maintained across the operating range by using open-loop Auto Frequency Calibration (AFC) tuning techniques and an adaptively biased bit-sliced charge pump. The PLL is capable of supporting spread spectrum clock (SSC) modulation with a low peak VCO gain by limiting its operation to the high gain region of the varactors where the capacitance versus voltage curves exhibit the greatest linearity. The VCOs support a frequency range of 4.0–4.8 GHz and 5.87–6.4 GHz. The 2-UI jitter of the forwarded clock at 6.4 Gb/s is 0.9 ps RMS while the long term acumulated <formula formulatype="inline"> <tex Notation="TeX">$N$</tex></formula>-UI jitter for large <formula formulatype="inline"> <tex Notation="TeX">$N$</tex></formula> is 2.1 ps RMS. </para>

Transceiver Macro with Spread-Spectrum Clocking Capability for AC-Coupled Cable Interfaces

A transceiver macro for high-speed data transmission via cable in vehicles is proposed. The transceiver uses ac coupling and bidirectional interface topology for protecting LSIs against unexpected short of cable and harness/chassis and has a spread-spectrum-clocking (SSC) generator that reduces noise due to electromagnetic interference. A driver current control has been used for fast switching of data direction on accoupled interfaces. An adaptive bandwidth control has been used in a ΔΣ PLL to improve SCC significantly. A test chip has been fabricated and shows stable and bi-directional data communication with data rate of 162 to 972 Mbps through 20-m cable. Thanks to an optimum calibration of the SSC-PLL bandwidth, it reduces peak power at 33kHz by -23dB and provides 2% modulation at a data rate of 810Mbps.

A Fully Integrated Spread-Spectrum Clock Generator by Using Direct VCO Modulation

A compact architecture for a fully-integrated spread- spectrum clock generator (SSCG) using voltage-controlled oscillator direct modulation is presented in this paper. A dual-path loop filter in the phase-locked loop is employed to reduce the size of the capacitance in the filter with the aid of an extra charge pump and a unity gain amplifier. At the same time, a third-charge pump which generates triangular waves is used to perform the function of a spread-spectrum. The proposed circuit has been fabricated using a 0.35-mum CMOS single-poly quadruple-metal process. The clock rate from 50 to 480 MHz with a center spread range of between 0.5% and 2% are verified and are close to the theoretical analyses. The size of the chip area is 0.82 x 0.8 mm2 (including the loop filter) and the power consumption was 27.5 mW at 400 MHz.

A High Performance Spread Spectrum Clock Generator Using Two-Point Modulation Scheme

A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order ΣΔ modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35μm CMOS process. The clock of 400MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73dB for the case of 2.5%. The size of chip area is 0.90×0.89mm2.

Electronically tunable pulse generator with programmable pulse repetition rate for 6.0 8.5 GHz ultra‐wideband communications

AbstractAn ultra‐wideband (UWB) carrier based pulse generator with tunable carrier frequency for 6.0–8.5 GHz UWB communications compliant to European and United States indoor regulations is presented. Pulses with a pulsewidth of 2.5 ns are generated using D‐type flip‐flops and are upconverted by a frequency mixer and a tunable voltage controlled oscillator providing a carrier frequency of 6.6–7.9 GHz. For the generation of pulse trains, a pulse repetition rate of up to 333 MHz is realized using a programmable clock multiplier offering optional spread spectrum clocking to smooth the output spectrum. Suitable modulation formats are pulse position modulation and on‐off‐keying which can be easily implemented by changing baseband data. Measurement results in time domain and frequency domain are presented showing the functionality of the fabricated device and its conformity to European and US UWB regulations. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1649–1651, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23462

A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.4 × 1.4 mm2 in a 0.18-μm CMOS process and consumes 52 mW.

A Wide-Tracking Range Clock and Data Recovery Circuit

A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 mum CMOS process achieves BER <10-12 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.

Conducted EMI Reduction in Power Converters by Means of Periodic Switching Frequency Modulation

Spread spectrum clock generation techniques were originally developed to reduce electromagnetic interference (EMI) in communications and microprocessor systems working in the range of hundreds of megahertz. Nowadays, the switching frequency of power converters has been increasing up to values that make worthy the application of such switching frequency modulation techniques to reduce EMI emissions in power converters. Although random modulations have been applied before to power converters, periodic patterns can provide some advantages. First, theoretical principles of frequency modulation using three periodic patterns for the modulating function are presented. The influence of some important modulation parameters on the EMI reduction is analyzed and some considerations about the EMI filters design are also presented. The effectiveness of such methods in terms of EMI reduction is demonstrated theoretically and confirmed with experimental results obtained from tests carried out on two converters. The first one is a 2.5 W buck converter that can be switched up to 1 MHz and the second one is a 600 W boost converter switching at 40 kHz. In both cases, attenuations obtained in conducted EMI are evaluated. Finally, special attention has been paid to input current and output voltage ripple in order to evaluate possible undesired side-effects produced by this technique.

A Low-Jitter Spread Spectrum Clock Generator Using FDMP

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A 1.5 GHz spread spectrum clock generator (SSCG) is realized by a fractional N frequency synthesizer with a third-order delta-sigma modulator and a fractional dual-modulus prescaler (FDMP). This FDMP utilizes a fractional division ratio to have a small phase step to improve the jitter performance. This SSCG has been fabricated in a 0.18 um CMOS process, and it consumes 34.2 mW from a supply of 1.8 V. The measured rms jitter is 5.55 ps and the measured electromagnetic interference reduction amount is 14.77 dB. The measured phase noise is <formula formulatype="inline"><tex>$-97.18$</tex></formula> dBc/Hz at 1 MHz offset. </para>

Impact of Frequency-Modulated Harmonic Noises From PCs on OFDM-Based WLAN Systems

Theoretical and numerical analyses are conducted on the bit error rate (BER) of orthogonal frequency division multiplexing (OFDM)-based wireless LAN (WLAN) systems that are subjected to electromagnetic interference (EMI) caused by radiated noises from personal computers (PCs). The aim of the analysis is to investigate the impact of frequency- modulated harmonic noises generated by spread-spectrum clock (SSC) systems in PCs. SSC techniques are commonly employed in order to reduce the spectral amplitude of clock harmonics measured in EMI compliance tests. The results of the analysis revealed that: (1) BER can be seriously affected in an actual situation where a WLAN antenna installed in or placed very close to a PC receives noise generated by the PC itself; (2) the forward error correction (FEC) in IEEE802.11 a/g becomes less effective as the frequency variation rate of the harmonic increases; and (3) frequency-modulated clock harmonics have a greater negative effect on BER than unmodulated harmonics do. Thus, SSC does not necessarily reduce the impact of clock harmonics on OFDM-based WLAN systems, even if the spectral amplitude of the harmonics is reduced. The impact of clock harmonics on WLAN is compared with that of other wideband noises. Discussion is further extended to cover how to mitigate the interference.

All Digital Spread Spectrum Clock Generator for EMI Reduction

An effective solution to control electromagnetic interference in computing appliances such as DVD players or home theater systems is to apply modulation on the system clock. The presence of modulation on the clock reduces the radiated power per unit bandwidth. We present the implementation of a spread spectrum clock generator (SSCG) using strictly digital components. A digital delay line (DDLi) controlled by a small digital circuit is used to increase or decrease the delay on a clock and hence create a modulated output. The DDLi total electrical length is no longer than one period of the 27-MHz reference clock as the digital circuit can adjust to the limited length of the line. The circuit can produce up or down spread by modulating the frequency of the reference with a triangular waveform. The measured peak power reduction is greater than 13 dB for a deviation of about 3% and a frequency modulation of 100 kHz. A real-time digital calibration circuit enables a process and temperature independent operation. The circuit occupies 0.06 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 0.15-mum CMOS process and consumes 7.1 mW

Interference potential of PC noises on MB-OFDM UWB systems

Since PC noises in the UWB frequency band mainly comprise the harmonics of clock signals, a numerical analysis is made on the influence of clock harmonics on the bit error rate (BER) of multiband OFDM (MB-OFDM) UWB systems. Results show that clock harmonics cause a considerable BER degradation when a UWB terminal is placed close to a PC. They further show that frequency modulation of a PC clock signal, so-called spread spectrum clocking (SSC), has no effect for mitigating BER degradation, though SSC techniques are commonly used in PCs for reducing the power spectral density of radiated clock harmonic noises

Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit Modulator-Controlled Fractional PLL

We have developed a spread-spectrum Phase-Locked Loop (PLL) for serial Advanced Technology Attachment (ATA) applications. We investigated the relation between the output jitter of PLLs in serial ATA applications and ΣΔ modulators in PLLs. On the basis of this study, we developed a spread-spectrum PLL for serial ATA applications and achieved a combination of small jitter and large electromagnetic interference (EMI) peak power reduction. This was achieved using two key components: multi-bit SA-controlled PLL and voltage-controlled oscillation with cross-coupled load delay cells. Using a 0.15-μm complementary metal-oxide semiconductor process, we fabricated a complete serial ATA transceiver featuring a spread-spectrum clock generator (SSCG). We achieved a spread-spectrum PLL with 10-dB EMI reduction and 8.1 ps random jitter for use in serial ATA applications. All other measured results for SSCG performance were very good and showed that the spread-spectrum generator more than satisfies serial ATA specifications.

Evaluation of BER in Bluetooth Wireless Systems Disturbed by Radiated Noise from Spread Spectrum Clock Systems

Frequency-modulated clock signals are widely used in personal computers to reduce the amplitude of the clock harmonic noise, as measured using an electromagnetic interference (EMI) test receiver. However, the power of the clock harmonics is not decreased with this technique called spread spectrum clocking (SSC). Hence, the impact of the harmonics of a frequency-modulated clock on the bit error rate (BER) and packet error rate (PER) of a Bluetooth system is theoretically analyzed. In addition, theoretical analysis covers the effectiveness of a frequency hopping spread spectrum (FH-SS) scheme and forward error correction (FEC) in mitigating the degradation in the BER and PER caused by clock harmonic interference. The results indicate that the BER and PER strongly depend on the modulating frequency and maximum frequency deviation of the clock harmonic. They also indicate that radiated clock harmonics may considerably degrade the BER and PER when a Bluetooth receiver is very close to a personal computer. Frequency modulating the clock harmonics slightly reduces the BER while it negligibly reduces the PER.