A 4–6.4 GHz LC PLL With Adaptive Bandwidth Control for a Forwarded Clock Link

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A wide range differentially tuned LC PLL using dual switched capacitor VCOs was designed in a 65 nm standard CMOS process for a forwarded clock link. Bandwidth and stability were maintained across the operating range by using open-loop Auto Frequency Calibration (AFC) tuning techniques and an adaptively biased bit-sliced charge pump. The PLL is capable of supporting spread spectrum clock (SSC) modulation with a low peak VCO gain by limiting its operation to the high gain region of the varactors where the capacitance versus voltage curves exhibit the greatest linearity. The VCOs support a frequency range of 4.0–4.8 GHz and 5.87–6.4 GHz. The 2-UI jitter of the forwarded clock at 6.4 Gb/s is 0.9 ps RMS while the long term acumulated <formula formulatype="inline"> <tex Notation="TeX">$N$</tex></formula>-UI jitter for large <formula formulatype="inline"> <tex Notation="TeX">$N$</tex></formula> is 2.1 ps RMS. </para>